From patchwork Wed Mar 31 10:58:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12175223 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC9AEC433DB for ; Wed, 31 Mar 2021 11:02:02 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 173EF61990 for ; Wed, 31 Mar 2021 11:02:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 173EF61990 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=HIrvkLaH/cr6uUDNZX0rjfIQFvPPZ2pFps7r3A8Y3lY=; b=TDXqU0+pB7GfJMDsAxqH8sYXST o5LVDJT5Ko8zDh1Sa3n9fk1AM2BJAHj75XFxAZEryi1ySFjBjlRgnch4+2yoWM4J+z1jc8B4XtQwh /cHVomnmCZtip1Aprkr6SA0RZSuNkGj2+V/w1P3tncT81nhcWcXtAhWBM4kj1XmchUVhykTMdrQaV toKgk6uRV59fL2pcxhLGY12GC6ggOdTGTjhjKIz7vq5kKmOf417bploPN2JY3zWjN6X48nYUHyjhe Dc5W1Bgq2xNLP/Jzdj9XgbYG33GrkrAX8roIxtkFpS5973nvy88DAWD16gh3hz2swDj6Ir0NLhG7f pPPxqjLA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRYZK-006JKj-88; Wed, 31 Mar 2021 10:59:27 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRYZA-006JJV-5g for linux-arm-kernel@lists.infradead.org; Wed, 31 Mar 2021 10:59:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617188355; x=1648724355; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=tV1IHHwxHo+23pny/S3PfV0lwm90D0exK7+vUd55pmU=; b=KDt8O1ocglza4A+mzu5ixJmRVHURfmSWb+1YfB6d8swLE4nHGFHZGhmx ErdA3vF113Y34mAtI408mYuFLceyTzKL7ogSMOoh0dBCpfO8Vh0XeTlT7 RwmKaz3GUONsHQRcYlhyA4EPb9IutWPqHjLEXyPdSz+BOo1PCjKJcevVf pFL1rBmbAmCFpyfVt83XYtYux6YEK5YQ/O/vP3z6qBQnXTOvRkTWJHDO+ pAPvlK2J2sUUH8pnXcRpOtL3HgdSa3sITboKUu5w6djprznAOfevoLAUS HSEiyxHhgnXvEc4F1kkiSwb4v0nZ2mtguIQxDuiFjrMIU4E+f8hO53+6+ A==; IronPort-SDR: wq8NtblxQ506lJV4tYzPoCJavkrGMtoLFq1E+Mf2u0dpBnpJa5sJN30E2XLSFx55dC1dK0Tc0B o5oRuT7kHw7QVyJK6ggX0RKM84gWrMsshs6v8qspcs5WROJWYsEw8NehMfadFUOsfDUYHDV415 pihJPZPAAkw7Zbu2IsisiFFrj0xIoF9/FPKo+CVkfyK4GOJO7TPOPuZ5jPodj63LwK9M23A9kA ofUnl/zXJjPYtCu00tMDEzkdKe6HI7Yp6bl6Ht+maQzydlb7SXGu/wcS9C8EGGOQSHuCkvv0Mc Hgc= X-IronPort-AV: E=Sophos;i="5.81,293,1610434800"; d="scan'208";a="115333279" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 31 Mar 2021 03:59:12 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Wed, 31 Mar 2021 03:59:12 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Wed, 31 Mar 2021 03:59:10 -0700 From: Claudiu Beznea To: , , , , CC: , , , Claudiu Beznea Subject: [PATCH 00/24] ARM: at91: pm: add support for sama7g5 Date: Wed, 31 Mar 2021 13:58:44 +0300 Message-ID: <20210331105908.23027-1-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210331_115917_155554_1E64FF3C X-CRM114-Status: GOOD ( 10.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, This series adds PM support for SAMA7G5. The standby, ulp0, ulp1, and backup modes are supported. Thank you, Claudiu Beznea Claudiu Beznea (23): ARM: at91: pm: move pm_bu to soc_pm data structure ARM: at91: pm: move the setup of soc_pm.bu->suspended ARM: at91: pm: document at91_soc_pm structure ARM: at91: pm: check for different controllers in at91_pm_modes_init() ARM: at91: pm: do not initialize pdev ARM: at91: pm: use r7 instead of tmp1 ARM: at91: pm: avoid push and pop on stack while memory is in self-refersh ARM: at91: pm: s/CONFIG_SOC_SAM9X60/CONFIG_HAVE_AT91_SAM9X60_PLL/g ARM: at91: pm: add support for waiting MCK1..4 ARM: at91: sfrbu: add sfrbu registers definitions for sama7g5 ARM: at91: ddr: add registers definitions for sama7g5's ddr ARM: at91: pm: add self-refresh support for sama7g5 ARM: at91: pm: add support for MCK1..4 save/restore for ulp modes ARM: at91: pm: add support for 2.5V LDO regulator control ARM: at91: pm: wait for ddr power mode off dt-bindings: atmel-sysreg: add bindings for sama7g5 ARM: at91: pm: add sama7g5 ddr controller ARM: at91: pm: add sama7g5 ddr phy controller ARM: at91: pm: save ddr phy calibration data to securam ARM: at91: pm: add backup mode support for SAMA7G5 ARM: at91: pm: add sama7g5's pmc ARM: at91: pm: add pm support for SAMA7G5 ARM: at91: pm: add sama7g5 shdwc Eugen Hristev (1): ARM: at91: sama7: introduce sama7 SoC family .../devicetree/bindings/arm/atmel-sysregs.txt | 15 +- arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/generic.h | 2 + arch/arm/mach-at91/pm.c | 343 ++++++-- arch/arm/mach-at91/pm.h | 3 + arch/arm/mach-at91/pm_data-offsets.c | 2 + arch/arm/mach-at91/pm_suspend.S | 827 +++++++++++++----- arch/arm/mach-at91/sama7.c | 49 ++ include/soc/at91/sama7-ddr.h | 80 ++ include/soc/at91/sama7-sfrbu.h | 34 + 10 files changed, 1066 insertions(+), 290 deletions(-) create mode 100644 arch/arm/mach-at91/sama7.c create mode 100644 include/soc/at91/sama7-ddr.h create mode 100644 include/soc/at91/sama7-sfrbu.h