Message ID | 20210517203724.1006254-1-martin.blumenstingl@googlemail.com (mailing list archive) |
---|---|
Headers | show |
Series | clk: meson: rounding for fast clocks on 32-bit SoCs | expand |
On Mon 17 May 2021 at 22:37, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the > fast HDMI PLL and it's OD (post-dividers). This clock tree can run at > up to approx. 3GHz. > This however causes a problem, because these rates require BIT(31) to > be usable. Unfortunately this is not the case with clk_ops.round_rate > on 32-bit systems. BIT(31) is reserved for the sign (+ or -). > > clk_ops.determine_rate does not suffer from this limitation. It uses > an int to signal any errors and can then take all availble 32 bits for > the clock rate. > > I am sending this as RFC to start a discussion whether: > - this is a good way to solve it? .determine_rate() was meant to replace .round_rate() so I guess it is good to do it :) > - what are the alternatives? I don't see any ATM. Even with determine_rate(), 4.29GHz limitation seems a bit low nowadays. In AML SoC, most PLLs should be able to reach 6GHz ... hopefully we won't need that on the 32bits variant ;) > - getting some feedback on areas that need to be improved > > > As always: any feedback is welcome! > Overall, looks good to me. > > Thank you! > Martin > > > Martin Blumenstingl (3): > clk: divider: Add re-usable determine_rate implementations > clk: meson: regmap: switch to determine_rate for the dividers > clk: meson: pll: switch to determine_rate for the PLL ops > > drivers/clk/clk-divider.c | 39 +++++++++++++++++++++++++++++++++- > drivers/clk/meson/clk-pll.c | 26 +++++++++++++---------- > drivers/clk/meson/clk-regmap.c | 19 ++++++++--------- > include/linux/clk-provider.h | 6 ++++++ > 4 files changed, 68 insertions(+), 22 deletions(-)
Hi Jerome, On Tue, May 18, 2021 at 9:37 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > > > On Mon 17 May 2021 at 22:37, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > > > On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the > > fast HDMI PLL and it's OD (post-dividers). This clock tree can run at > > up to approx. 3GHz. > > This however causes a problem, because these rates require BIT(31) to > > be usable. Unfortunately this is not the case with clk_ops.round_rate > > on 32-bit systems. BIT(31) is reserved for the sign (+ or -). > > > > clk_ops.determine_rate does not suffer from this limitation. It uses > > an int to signal any errors and can then take all availble 32 bits for > > the clock rate. > > > > I am sending this as RFC to start a discussion whether: > > - this is a good way to solve it? > > .determine_rate() was meant to replace .round_rate() so I guess it is > good to do it :) ah, now things make more sense. thanks for the background info > > - what are the alternatives? > > I don't see any ATM. Even with determine_rate(), 4.29GHz limitation > seems a bit low nowadays. In AML SoC, most PLLs should be able to reach > 6GHz ... hopefully we won't need that on the 32bits variant ;) according to the public datasheet the maximum PLL frequency is at around 3GHz so I also hope that we're safe with this Martin