| Message ID | 20210608102547.4880-1-steven_lee@aspeedtech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | ASPEED sgpio driver enhancement. | expand |
On Tue, Jun 8, 2021 at 12:26 PM Steven Lee <steven_lee@aspeedtech.com> wrote: > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that > supports up to 80 pins. > In the current driver design, the max number of sgpio pins is hardcoded > in macro MAX_NR_HW_SGPIO and the value is 80. > > For supporting sgpio master interfaces of AST2600 SoC, the patch series > contains the following enhancement: > - Convert txt dt-bindings to yaml. > - Update aspeed-g6 dtsi to support the enhanced sgpio. > - Define max number of gpio pins in ast2600 platform data. Old chip > uses the original hardcoded value. > - Support muiltiple SGPIO master interfaces. > - Support up to 128 pins. > - Support wdt reset tolerance. > - Fix irq_chip issues which causes multiple sgpio devices use the same > irq_chip data. > - Replace all of_*() APIs with device_*(). > > Changes from v4: v5 looks good to me! I just need Rob's or another DT persons nod on the bindings (or timeout) before I merge it. Poke me if nothing happens. > ARM: dts: aspeed-g6: Add SGPIO node. > ARM: dts: aspeed-g5: Remove ngpios from sgpio node. These two need to be merged through the SoC tree, the rest I will handle. Yours, Linus Walleij
The 06/09/2021 18:54, Linus Walleij wrote: > On Tue, Jun 8, 2021 at 12:26 PM Steven Lee <steven_lee@aspeedtech.com> wrote: > > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one > > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that > > supports up to 80 pins. > > In the current driver design, the max number of sgpio pins is hardcoded > > in macro MAX_NR_HW_SGPIO and the value is 80. > > > > For supporting sgpio master interfaces of AST2600 SoC, the patch series > > contains the following enhancement: > > - Convert txt dt-bindings to yaml. > > - Update aspeed-g6 dtsi to support the enhanced sgpio. > > - Define max number of gpio pins in ast2600 platform data. Old chip > > uses the original hardcoded value. > > - Support muiltiple SGPIO master interfaces. > > - Support up to 128 pins. > > - Support wdt reset tolerance. > > - Fix irq_chip issues which causes multiple sgpio devices use the same > > irq_chip data. > > - Replace all of_*() APIs with device_*(). > > > > Changes from v4: > > v5 looks good to me! > > I just need Rob's or another DT persons nod on the bindings (or timeout) > before I merge it. Poke me if nothing happens. > > > ARM: dts: aspeed-g6: Add SGPIO node. > > ARM: dts: aspeed-g5: Remove ngpios from sgpio node. > > These two need to be merged through the SoC tree, the rest I will handle. > Hi Linus, Andrew, Per the comment in the following mail https://lkml.org/lkml/2021/6/9/317 I was wondering if I should prepare v6 for the currnet solution or I should drop this patch series then prepare another patch for the new solution(piar GPIO input/output) which breaks userspace but is better than the current solution. Thanks, Steven > Yours, > Linus Walleij
On Thu, Jun 10, 2021 at 4:24 AM Steven Lee <steven_lee@aspeedtech.com> wrote: > Per the comment in the following mail > https://lkml.org/lkml/2021/6/9/317 > > I was wondering if I should prepare v6 for the currnet solution or > I should drop this patch series then prepare another patch for the > new solution(piar GPIO input/output) which breaks userspace but is > better than the current solution. I would say just go ahead with the new solution. AFAIK Aspeed has pretty tight control over what kind of userspace run on these systems. BTW please influence Aspeed to use the GPIO character device and ligpiod https://git.kernel.org/pub/scm/libs/libgpiod/libgpiod.git/ if you are doing any kind of userspace GPIO control (which I suspect that you do). Yours, Linus Walleij
The 06/10/2021 15:50, Linus Walleij wrote: > On Thu, Jun 10, 2021 at 4:24 AM Steven Lee <steven_lee@aspeedtech.com> wrote: > > > Per the comment in the following mail > > https://lkml.org/lkml/2021/6/9/317 > > > > I was wondering if I should prepare v6 for the currnet solution or > > I should drop this patch series then prepare another patch for the > > new solution(piar GPIO input/output) which breaks userspace but is > > better than the current solution. > > I would say just go ahead with the new solution. AFAIK Aspeed > has pretty tight control over what kind of userspace run on these > systems. > > BTW please influence Aspeed to use the GPIO character device > and ligpiod > https://git.kernel.org/pub/scm/libs/libgpiod/libgpiod.git/ > if you are doing any kind of userspace GPIO control (which I > suspect that you do). > We currently use gpioset and gpioget that provided by libgpiod to test aspeed gpio and sgpio drivers. For the current solution on AST2600, the valid range of input pins is 0 ~ 127, the valid range of output pins is 128 ~ 255. So we access input pins by the following command ``` gpioget $chipId 0 1 2 3 4 ... 127 ``` and access output pins by the following command ``` gpioset $chipId 128=1 129=0 130=1 131=1 ... 255=1 ``` The new solution will change the gpio id order as follows Input: ``` gpioget $chipId 0 2 4 6 8 ... 254 ``` Output: ``` gpioset $chipId 1=1 3=0 5=1 7=1 ... 255=1 ``` Thanks, Steven > Yours, > Linus Walleij