From patchwork Fri Oct 15 16:14:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 12562429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A689EC433EF for ; Fri, 15 Oct 2021 16:16:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7015761053 for ; Fri, 15 Oct 2021 16:16:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7015761053 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=/JFUZJJiQ58F7UNgWOl2W2Gp+tn0YeEO2bNjysR9Bfg=; b=UFDcWFjfNUhoBC rO54PAnGIo4eJ/91T2vVgV+JsHzzj5J7hboum9CxL/x8cYvRxF+1nz8L13q4+BPLyLnLoQ4kX3MzS WqRmNDTLMFxhFv1qZjd0JAXkWbYRKtVmDdHSipTPMlXeZI8oN/mTJnBOsBaC4pv6VlqmOXJIAxgho wXcTyAagRI16QgCp8wLFhrhGSd9b1S+oFPaeUSK3AGhMaWp6kVoZGDmS6Ax/2g0nPBx9QfHfdklRl 97SauIf2RqsLweY76CDX/u8ahAQM5P4xVwz5XcR3v6tX7YXjWUO9OS2IsBDQ2gAMrp0H2jAaUM6k/ nniWpCAWzuFug+IWSNlg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mbPr0-0081YZ-PG; Fri, 15 Oct 2021 16:14:42 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mbPqx-0081Y9-2J for linux-arm-kernel@lists.infradead.org; Fri, 15 Oct 2021 16:14:40 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 68B2C11D4; Fri, 15 Oct 2021 09:14:35 -0700 (PDT) Received: from merodach.members.linode.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9CC923F66F; Fri, 15 Oct 2021 09:14:34 -0700 (PDT) From: James Morse To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu Cc: Will Deacon , Catalin Marinas , Marc Zyngier Subject: [RFC PATCH 0/7] arm64: mm: Prototype to allow drivers to request PBHA values Date: Fri, 15 Oct 2021 16:14:09 +0000 Message-Id: <20211015161416.2196-1-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211015_091439_242207_15E27FC6 X-CRM114-Status: GOOD ( 24.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello! Do you have hardware that uses PBHA? If so, what does the SoC do in response to which bits, and what workload needs that behaviour? This series is a start at trying to work out what linux needs to support to makeuse of existing SoCs using PBHA. PBHA is a feature that adds an extra four bits to each read or write transaction for the SoC implementer to do - whatever they like with! An obvious example would be a hint for whether the access should allocate (or not) in the system cache. The hint would allow better performance for some SoC specific workloads. The arm-arm doesn't define what the bits do, only where in the page tables they come from. It also doesn't define how these bits are combined between stage1 and stage2. It appears that all of Arm's Cortex cores with the feature do the stage1+stage2 combining in the same way. (stage2 wins). Patch 1 turns PBHA on for stage2, where KVM only generates the safe default value. This stops KVM guests from using PBHA on Cortex cores. It should be harmless for any core that does not behave like this. The remaining patches allow firmware to describe which PBHA bits only affect performance, and which have dangerous side effects like encryption or other forms of corruption, that would mean the OS has to ensure all aliases are removed. The lists exist to allow an OS to avoid the cost of rewriting aliases when that isn't necessary, and for KVM to determine which bits it can enable for a guest: KVM uses the 'performance only' list to try and enable the corresponding bits for KVM guests - but only if they can't be used to generate a value not in the list. This depends on knowing the CPU implements the 'stage2 wins' behaviour. I've listed the CPUs whose TRMs describe this behaviour, and asked for other TRMs to be updated to say what the behaviour is. A pgprot_pbha() helper is added to allow drivers to request the 'performance only' kind of PBHA bit for a mapping. Supporting the 'no aliases' kind is much more involved. I've not tried to do this. (do we need to?) I don't have a platform that uses any of this, so I can't detect whether or not the PBHA values were generated with the read/writes. Thanks, James Morse (7): KVM: arm64: Detect and enable PBHA for stage2 dt-bindings: Rename the description of cpu nodes cpu.yaml dt-bindings: arm: Add binding for Page Based Hardware Attributes arm64: cpufeature: Enable PBHA bits for stage1 arm64: mm: Add pgprot_pbha() to allow drivers to request PBHA values KVM: arm64: Configure PBHA bits for stage2 Documentation: arm64: Describe the support and expectations for PBHA Documentation/arm64/index.rst | 1 + Documentation/arm64/pbha.rst | 86 +++ .../devicetree/bindings/arm/cpu.yaml | 544 ++++++++++++++++ .../devicetree/bindings/arm/cpus.yaml | 591 ++---------------- arch/arm64/Kconfig | 13 + arch/arm64/include/asm/cpufeature.h | 1 + arch/arm64/include/asm/cputype.h | 4 + arch/arm64/include/asm/kvm_arm.h | 1 + arch/arm64/include/asm/kvm_pgtable.h | 9 + arch/arm64/include/asm/pgtable-hwdef.h | 5 + arch/arm64/include/asm/pgtable.h | 12 + arch/arm64/kernel/cpufeature.c | 196 ++++++ arch/arm64/kernel/image-vars.h | 3 + arch/arm64/kvm/hyp/pgtable.c | 15 +- arch/arm64/tools/cpucaps | 3 + 15 files changed, 961 insertions(+), 523 deletions(-) create mode 100644 Documentation/arm64/pbha.rst create mode 100644 Documentation/devicetree/bindings/arm/cpu.yaml