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[86.58.29.253]) by smtp.gmail.com with ESMTPSA id a141sm13776345wme.37.2021.11.19.23.34.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Nov 2021 23:34:52 -0800 (PST) From: Jernej Skrabec To: mripard@kernel.org, wens@csie.org Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 0/2] dts: Add CEC clock to DW HDMI Date: Sat, 20 Nov 2021 08:34:46 +0100 Message-Id: <20211120073448.32480-1-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.34.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211119_233454_935107_59CE43A4 X-CRM114-Status: GOOD ( 10.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Experimentation proved that CEC controller in H3-like DW-HDMI core depends on 32 kHz clock output from RTC. If board has external 32768 Hz crystal, HDMI CEC always work. However, if external crystal is missing and 32 kHz clock is generated by internal oscillator, CEC communication may or may not work, depending on accuracy. Changing internal oscillator prescaler can make CEC work. This was totally missed when implementing HDMI support, because user manual has no CEC information besides the fact that it exists. Please take a look. Best regards, Jernej Jernej Skrabec (2): arm64: dts: allwinner: a64: Add CEC clock to HDMI ARM: dts: sunxi: Add CEC clock to DW-HDMI arch/arm/boot/dts/sun8i-r40.dtsi | 4 ++-- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 4 ++-- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-)