From patchwork Thu Dec 9 04:32:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Martin X-Patchwork-Id: 12695435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38B1AC433F5 for ; Thu, 9 Dec 2021 04:35:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=SbqthJaH+GnvoihjA5NMnFgWbaE/MfKXfQ4keIfYY6Y=; b=lrIca/irlD42YF 3oECPjZN3Jq/zMjHvRm+UeP47IdgopLnk58WAIavSVK+8rRRnSAfYzMQq2StfZanP6we2P9iatx0/ 2qzVF9Dgw0ie82XpcUJe1H+EmtfPUlI2tzIudiHNFRK/fgF0FUegFxoKnSo7ToH4/OwO5qWrCLPYV eWrgvMcHQpQXXd6f7OaloyxZi7j813ZT0FdUbNoaBjMR4v4CLtEEXjIR4FRL9OOEp7HRIKOct7YXu qKoEbuCsxxYnCg5abwxeGeLfv6dlCkttoif7ISTi4lahpkW/eoOuEpXs6UThVgDjGaAVia1htrDhO 8Hi5LpRVdn44Dk1bElYQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvB7X-00EsSI-LL; Thu, 09 Dec 2021 04:33:27 +0000 Received: from marcansoft.com ([212.63.210.85] helo=mail.marcansoft.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvB7T-00EsQ7-45 for linux-arm-kernel@lists.infradead.org; Thu, 09 Dec 2021 04:33:25 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: hector@marcansoft.com) by mail.marcansoft.com (Postfix) with ESMTPSA id 98D9E41E64; Thu, 9 Dec 2021 04:33:13 +0000 (UTC) From: Hector Martin To: Thomas Gleixner , Marc Zyngier , Rob Herring Cc: Hector Martin , Sven Peter , Alyssa Rosenzweig , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 0/6] irqchip/apple-aic: Add support for AICv2 Date: Thu, 9 Dec 2021 13:32:43 +0900 Message-Id: <20211209043249.65474-1-marcan@marcan.st> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211208_203323_342663_CB32694C X-CRM114-Status: GOOD ( 17.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi folks, In the t6000/t6001 (M1 Pro / Max) SoCs, Apple introduced a new version of their interrupt controller. This is a significant departure from AICv1 and seems designed to better scale to larger chips. This series adds support for it to the existing AIC driver. Gone are CPU affinities; instead there seems to be some kind of "automagic" dispatch to willing CPU cores, and cores can also opt-out via an IMP-DEF sysreg (!). Right now the bootloader just sets up all cores to accept IRQs, and we ignore all this and let the magic algorithm pick a CPU to accept the IRQ. In the future, we might start making use of these finer-grained capabilities for e.g. better real-time guarantees (CPUs running RT threads might opt out of IRQs). Legacy IPI support is also gone, so this implements Fast IPI support. Fast IPIs are implemented entirely in the CPU core complexes, using FIQs and IMP-DEF sysregs. This is also supported on t8103/M1, so we enable it there too, but we keep the legacy AIC IPI codepath in case it is useful for backporting to older chips. This also adds support for multi-die AIC2 controllers. While no multi-die products exist yet, the AIC2 in t600x is built to support up to 2 dies, and it's pretty clear how it works, so let's implement it. If we're lucky, when multi-die products roll around, this will let us support them with only DT changes. In order to support the extra die dimension, this introduces a 4-argument IRQ phandle form (3-argument is always supported and just implies die 0). All register offsets are computed based on capability register values, which should allow forward-compatibility with future AIC2 variants... except for one. For some inexplicable reason, the number of actually implemented die register sets is nowhere to be found (t600x has 2, but claims 1 die in use and 8 dies max, neither of which is what we need), and this is necessary to compute the event register offset, which is page-aligned after the die register sets. We have no choice but to stick this offset in the device tree... which is the same thing Apple do in their ADT. Hector Martin (6): dt-bindings: interrupt-controller: apple,aic: Add apple,aic2 support irqchip/apple-aic: Add Fast IPI support irqchip/apple-aic: Switch to irq_domain_create_tree and sparse hwirqs irqchip/apple-aic: Dynamically compute register offsets irqchip/apple-aic: Support multiple dies irqchip/apple-aic: Add support for AICv2 .../interrupt-controller/apple,aic.yaml | 62 ++- drivers/irqchip/irq-apple-aic.c | 419 ++++++++++++++---- 2 files changed, 393 insertions(+), 88 deletions(-)