[0/2] perf: arm_spe: make the PMSCR CX bit[3] consistent across the session

Message

German Gomez Jan. 13, 2022, 5:54 p.m. UTC

The value of the CX bit of the PMSCR register is not consistent across
a perf session. There is an example in [1/2] to reproduce the issue.

This cset applies a small correction to fix the consistency issue.

- [PATCH 1/2] Makes the CX bit consistent by caching the value during
  the initialization of the SPE PMU event.
- [PATCH 2/2] Allows CONTEXT packets when profiling in CPU mode.

German Gomez (2):
  perf: arm_spe: make the PMSCR CX bit[3] consistent across the session
  perf: arm_spe: Enable CONTEXT packets if profiling in CPU mode

 drivers/perf/arm_spe_pmu.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Comments

German Gomez Jan. 14, 2022, 9:31 a.m. UTC | #1

Apologies everyone, this was a missend.

On 13/01/2022 17:54, German Gomez wrote:
> The value of the CX bit of the PMSCR register is not consistent across
> a perf session. There is an example in [1/2] to reproduce the issue.
>
> This cset applies a small correction to fix the consistency issue.
>
> - [PATCH 1/2] Makes the CX bit consistent by caching the value during
>   the initialization of the SPE PMU event.
> - [PATCH 2/2] Allows CONTEXT packets when profiling in CPU mode.
>
> German Gomez (2):
>   perf: arm_spe: make the PMSCR CX bit[3] consistent across the session
>   perf: arm_spe: Enable CONTEXT packets if profiling in CPU mode
>
>  drivers/perf/arm_spe_pmu.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
>