From patchwork Thu Jan 27 12:20:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 12726712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEFD5C433F5 for ; Thu, 27 Jan 2022 12:22:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=Sr5t2tWocye+RVkmrIqgLo+AjSit050OTcrhUv3A99I=; b=Jd51aetfvifJaz bceWHa8a8Ht92Ag3by7fTF94zgc9Gl7S7T6CnmehRNhdQAyW3CR+fxTqXrHdCYvD0tJbIw8aitDFA EY04b4UHyNOmUbvDdE/HFuXoSK4D49+BZMy07pu5FpYf3PV4aMGU7qM5+GRdHfht921qk8DetmTXL zM2hLQhil/Bax3piZFhYK822Q6bmmtJk0FQCXMnQrzgNU3YeN9vKOToviX5SKoU4iw0+pppZYWADV Og2mTpG/S0dsvP06NJPukcpXs0dEsifG5zjzosGNw2Sy+OT0o3frblnxv7+DCfw7Mg0BXCMxyekQI A7hT/fVACg/J7W/mqnQA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nD3m2-00Fdsb-Fm; Thu, 27 Jan 2022 12:21:10 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nD3ly-00FdrY-DW for linux-arm-kernel@lists.infradead.org; Thu, 27 Jan 2022 12:21:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 835B3113E; Thu, 27 Jan 2022 04:21:05 -0800 (PST) Received: from eglon.cambridge.arm.com (unknown [10.1.196.218]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 669513F7D8; Thu, 27 Jan 2022 04:21:04 -0800 (PST) From: James Morse To: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Cc: Marc Zyngier , Catalin Marinas , Will Deacon , Alexandru Elisei , Suzuki K Poulose , Anshuman Khandual Subject: [PATCH v2 0/4] KVM: arm64: A510 errata workaround and fixes for fixup_guest_exit() Date: Thu, 27 Jan 2022 12:20:48 +0000 Message-Id: <20220127122052.1584324-1-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220127_042106_539786_346F07F1 X-CRM114-Status: GOOD ( 12.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello! Changes since v1: * Moved the SPSR_EL2 fixup into a helper called earlier * Use final cap * Dropped the IS_ENABLED() check --- Early Cortex-A510 parts have a nasty erratum where two ERETs, pointer-auth and software step conspire to corrupt SPSR_EL2. A guest can only trigger this when it is being stepped by EL2, which gives EL2 the opportunity to work around the erratum. Patch 4 does this, the SDEN is available from: https://developer.arm.com/documentation/SDEN2397239/900 Patches 2 and 3 fix two issues with the adjacent code where a stale esr value could be used to alter the ELR_EL2 when an IRQ synchronises an SError, and when an HVC synchronises an SError, the HVC may be handled twice, (not just execute twice). There are three series that would add the Cortex-A510 part macros. I've picked Anshuman's patch that does this, on the assumption that makes someone's life easier. I haven't spotted that patch on the arm64/for-next/fixes branch, so I've not included the hash in the prerequisite field of the CC-stable. Let me know if you want this reposted once that value is known. This series is based on v5.17-rc1 and can be retrieved from: https://git.gitlab.arm.com/linux-arm/linux-jm.git a510_errata/kvm_bits/v2 Thanks, James Anshuman Khandual (1): arm64: Add Cortex-A510 CPU part definition James Morse (3): KVM: arm64: Avoid consuming a stale esr value when SError occur KVM: arm64: Stop handle_exit() from handling HVC twice when an SError occurs KVM: arm64: Workaround Cortex-A510's single-step and PAC trap errata Documentation/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 16 ++++++++++++++++ arch/arm64/include/asm/cputype.h | 2 ++ arch/arm64/kernel/cpu_errata.c | 8 ++++++++ arch/arm64/kvm/handle_exit.c | 8 ++++++++ arch/arm64/kvm/hyp/include/hyp/switch.h | 23 +++++++++++++++++++++-- arch/arm64/tools/cpucaps | 1 + 7 files changed, 58 insertions(+), 2 deletions(-)