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[v3,00/10] ARM: Introduce HPE GXP Architecture

Message ID 20220310195123.109359-1-nick.hawkins@hpe.com (mailing list archive)
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Series ARM: Introduce HPE GXP Architecture | expand

Message

Hawkins, Nick March 10, 2022, 7:51 p.m. UTC
From: Nick Hawkins <nick.hawkins@hpe.com>

Changes since v2:
 *Reduced size of changes, put them into pathset format

Changes since v1:
 *Fix compiler warnings

The GXP is the HPE BMC SoC that is used in the majority
of HPE Generation 10 servers. Traditionally the asic will
last multiple generations of server before being replaced.

Info about SoC:

  HPE GXP is the name of the HPE Soc. This SoC is used to implement
  many BMC features at HPE. It supports ARMv7 architecture based on
  the Cortex A9 core. It is capable of using an AXI bus to which
  a memory controller is attached. It has multiple SPI interfaces
  to connect boot flash and BIOS flash. It uses a 10/100/1000 MAC
  for network connectivity. It has multiple i2c engines to drive
  connectivity with a host infrastructure. The initial patches
  enable the watchdog and timer enabling the host to be able to
  boot.

Nick Hawkins (10):
  arch: arm: mach-hpe: Introduce the HPE GXP architecture
  arch: arm: configs: multi_v7_defconfig
  drivers: wdt: Introduce HPE GXP SoC Watchdog
  clocksource/drivers: Add HPE GXP timer
  dt-bindings: timer: Add HPE GXP Timer Binding
  dt-bindings: watchdog: Add HPE GXP Watchdog timer binding
  dt-bindings: arm: Add HPE GXP Binding
  dt-bindings: arm: Add HPE GXP CPU Init
  arch: arm: boot: dts: Introduce HPE GXP Device tree
  maintainers: Introduce HPE GXP Architecture

 .../cpu-enable-method/hpe,gxp-cpu-init.yaml   |  31 +++
 .../devicetree/bindings/arm/gxp.yaml          |  53 +++++
 .../bindings/timer/hpe,gxp-timer.yaml         |  45 +++++
 .../bindings/watchdog/hpe,gxp-wdt.yaml        |  37 ++++
 MAINTAINERS                                   |  14 ++
 arch/arm/Kconfig                              |   2 +
 arch/arm/Makefile                             |   1 +
 arch/arm/boot/dts/Makefile                    |   2 +
 arch/arm/boot/dts/hpe-bmc-dl360gen10.dts      |  27 +++
 arch/arm/boot/dts/hpe-gxp.dtsi                | 148 ++++++++++++++
 arch/arm/configs/multi_v7_defconfig           |   3 +
 arch/arm/mach-hpe/Kconfig                     |  20 ++
 arch/arm/mach-hpe/Makefile                    |   1 +
 arch/arm/mach-hpe/gxp.c                       |  61 ++++++
 drivers/clocksource/Kconfig                   |   8 +
 drivers/clocksource/Makefile                  |   1 +
 drivers/clocksource/gxp-timer.c               | 159 +++++++++++++++
 drivers/watchdog/Kconfig                      |   8 +
 drivers/watchdog/Makefile                     |   1 +
 drivers/watchdog/gxp-wdt.c                    | 191 ++++++++++++++++++
 20 files changed, 813 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/hpe,gxp-cpu-init.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/gxp.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
 create mode 100644 Documentation/devicetree/bindings/watchdog/hpe,gxp-wdt.yaml
 create mode 100644 arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
 create mode 100644 arch/arm/boot/dts/hpe-gxp.dtsi
 create mode 100644 arch/arm/mach-hpe/Kconfig
 create mode 100644 arch/arm/mach-hpe/Makefile
 create mode 100644 arch/arm/mach-hpe/gxp.c
 create mode 100644 drivers/clocksource/gxp-timer.c
 create mode 100644 drivers/watchdog/gxp-wdt.c

Comments

Arnd Bergmann March 11, 2022, 8:19 a.m. UTC | #1
On Thu, Mar 10, 2022 at 8:51 PM <nick.hawkins@hpe.com> wrote:
>
> From: Nick Hawkins <nick.hawkins@hpe.com>
>
> Changes since v2:
>  *Reduced size of changes, put them into pathset format
>
> Changes since v1:
>  *Fix compiler warnings
>
> The GXP is the HPE BMC SoC that is used in the majority
> of HPE Generation 10 servers. Traditionally the asic will
> last multiple generations of server before being replaced.
>
> Info about SoC:
>
>   HPE GXP is the name of the HPE Soc. This SoC is used to implement
>   many BMC features at HPE. It supports ARMv7 architecture based on
>   the Cortex A9 core. It is capable of using an AXI bus to which
>   a memory controller is attached. It has multiple SPI interfaces
>   to connect boot flash and BIOS flash. It uses a 10/100/1000 MAC
>   for network connectivity. It has multiple i2c engines to drive
>   connectivity with a host infrastructure. The initial patches
>   enable the watchdog and timer enabling the host to be able to
>   boot.

This looks much better already, thanks for following the normal
submission procedures. With the timing for the merge window, this
is now too late for 5.18, but let's try to get it into 5.19 then.

       Arnd