From patchwork Tue Apr 5 11:27:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12801447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B61B0C433FE for ; Tue, 5 Apr 2022 11:26:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=TTN8vnSNV0PqJj7BKRdP/l3O92D9Hda469vcCQOqZBA=; b=zZDrz8kmHfW2+N 9GBpMhCs1S7H0Kh4X/LltP0PS1qaOD4bT+LyTM4/X2mtUXbs7EuYsHqFyiEDQKT6oERPOwTXbZVZQ 5X355znl4c28Au42MiCDx2yIMRbgzayaSVptpNpRNtFWUDSs1Eb3daH5G4QQTUabYpYVldL75YAzX BrZj0vt6MWenANaVHNAmWD9tuXqEnHFxp7jgPPAxQAionT70h76wKLUXB6ZOFw+Thp5YqwZKVDRR6 ij5dnjeVo3OqHv83IOUSQvYkFjRNSn6UZOsE8aWIdkihFO1+um8IMJ7vo7FB8oU5ApMgQi7MV3/PY cFh63mr5ztY21u3otkuA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nbhJS-000mhv-Mt; Tue, 05 Apr 2022 11:25:30 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nbhJO-000mfl-Mx for linux-arm-kernel@lists.infradead.org; Tue, 05 Apr 2022 11:25:28 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649157926; x=1680693926; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=7o0sgXENCg/Y0DQNqjlqJ8tcLEzSZooqtxoe6odT57w=; b=y6nCvi9Xh42nK0EJhegwpB0CZgtfjYv8s/cBj7leaFoAe9qeQEwiehMc QLyzYYt0osL0zFouBHw1u9w4Zx1oezWIYlHxiSmbewhgd91nDUTvoCvyY Th09SSbsOiBuDku/evR7/+Fl8FIMIcPEj6iusfDjAaMKlJueqEKticQf3 AmtWNxGTCRJ0SnvomSzPEfaSi3LYE9yjMydfyjMvUgd+tKJJyZqAQTBUe ScwNY7+kK1YQsOdvkEmCyhToWUfKHmGi21W9iY2EPhbdY7oi27Ucumluo tnvWx7AsYsTJpVnhqTOeqwvwX/wE7Qa4D1dpjnGKKWYT7PxPa0pkkZb8p g==; X-IronPort-AV: E=Sophos;i="5.90,236,1643698800"; d="scan'208";a="159346885" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Apr 2022 04:25:22 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 5 Apr 2022 04:25:22 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 5 Apr 2022 04:25:20 -0700 From: Claudiu Beznea To: , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 0/8] power: reset: at91-reset: add support for sama7g5 Date: Tue, 5 Apr 2022 14:27:16 +0300 Message-ID: <20220405112724.2760905-1-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220405_042526_795577_64BB1CFC X-CRM114-Status: UNSURE ( 8.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, The series adds reset controller support for SAMA7G5 SoCs. Compared with previous version the reset controller embedded on SAMA7G5 is able to reset individual on SoC devices (e.g. USB PHY controllers). Among with this I took the change and converted reset controller bindings to YAML (patch 2/8) and adapt reset controller nodes in device tree files to comply with DT specifications (patch 1/8). Thank you, Claudiu Beznea Claudiu Beznea (8): ARM: dts: at91: use generic name for reset controller dt-bindings: reset: convert Atmel/Microchip reset controller to YAML dt-bindings: reset: atmel,at91sam9260-reset: add sama7g5 bindings dt-bindings: reset: add sama7g5 definitions power: reset: at91-reset: add at91_reset_data power: reset: at91-reset: add reset_controller_dev support power: reset: at91-reset: add support for SAMA7G5 ARM: dts: at91: sama7g5: add reset-controller node .../devicetree/bindings/arm/atmel-sysregs.txt | 15 -- .../reset/atmel,at91sam9260-reset.yaml | 68 +++++++++ arch/arm/boot/dts/at91sam9260.dtsi | 2 +- arch/arm/boot/dts/at91sam9261.dtsi | 2 +- arch/arm/boot/dts/at91sam9263.dtsi | 2 +- arch/arm/boot/dts/at91sam9g45.dtsi | 2 +- arch/arm/boot/dts/at91sam9n12.dtsi | 2 +- arch/arm/boot/dts/at91sam9rl.dtsi | 2 +- arch/arm/boot/dts/at91sam9x5.dtsi | 2 +- arch/arm/boot/dts/sam9x60.dtsi | 2 +- arch/arm/boot/dts/sama5d2.dtsi | 2 +- arch/arm/boot/dts/sama5d3.dtsi | 2 +- arch/arm/boot/dts/sama5d4.dtsi | 2 +- arch/arm/boot/dts/sama7g5.dtsi | 7 + drivers/power/reset/at91-reset.c | 134 ++++++++++++++++-- include/dt-bindings/reset/sama7g5-reset.h | 10 ++ 16 files changed, 217 insertions(+), 39 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml create mode 100644 include/dt-bindings/reset/sama7g5-reset.h