From patchwork Tue May 3 16:33:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 12835978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E633C433FE for ; Tue, 3 May 2022 16:35:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=HddtoF9jfjc1urUoEpw/T+dv7D/4H33TqFC1l+Q2G3w=; b=3rKe9WoeIUjD0w jtOAqyvcg2V9WMhpTst3MQ2XjJohtL+r9dH+YZkwUT5w+fwJHe2+euJMGuF8AUDVoxsCIvYJ1bboH taacEvwxX0Ome5/jYRzmJuDLpPLxpLD2jHro4aO9JZIm9BJ4uKIbPw21O/KBS5fbgTxeFIEsXVe+w aenwTyv1Kt/7H+AwkdiVsqvjIwD02bhKicygDZzkgZLqM1BxWXy0XwffdFtDUK/LDOkcB7vC4axSz K59QkmbNK4kWTBcw0FW5GWMaK8kFY5C17Pa0nJyBE9nD3aOQoNTBtWy6O2l1qcq0KBs623xhSs4vu BjlHR5IRoAQDgCQUDAlg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlvTm-006kKZ-HZ; Tue, 03 May 2022 16:34:26 +0000 Received: from frasgout.his.huawei.com ([185.176.79.56]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nlvTi-006kFO-TE for linux-arm-kernel@lists.infradead.org; Tue, 03 May 2022 16:34:25 +0000 Received: from fraeml705-chm.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Kt57H5zF8z67MnZ; Wed, 4 May 2022 00:31:07 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml705-chm.china.huawei.com (10.206.15.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2375.24; Tue, 3 May 2022 18:34:11 +0200 Received: from A2006125610.china.huawei.com (10.202.227.178) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 3 May 2022 17:34:04 +0100 From: Shameer Kolothum To: , , CC: , , , , , , , , , , , , Subject: [PATCH v12 0/9] ACPI/IORT: Support for IORT RMR node Date: Tue, 3 May 2022 17:33:21 +0100 Message-ID: <20220503163330.509-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.202.227.178] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220503_093423_299031_F66BCAFF X-CRM114-Status: GOOD ( 21.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi v11 --> v12 -Minor fix in patch #4 to address the issue reported by the kernel test robot. -Added R-by tags by Christoph(patch #1) and Lorenzo(patch #4). -Added T-by from Steve to all relevant patches. Many thanks!. Please note, this series has a dependency on the ACPICA header patch here[1]. Please take a look and let me know. Thanks, Shameer [1] https://lore.kernel.org/all/44610361.fMDQidcC6G@kreacher/ From old: We have faced issues with 3408iMR RAID controller cards which fail to boot when SMMU is enabled. This is because these controllers make use of host memory for various caching related purposes and when SMMU is enabled the iMR firmware fails to access these memory regions as there is no mapping for them. IORT RMR provides a way for UEFI to describe and report these memory regions so that the kernel can make a unity mapping for these in SMMU. Change History: v10 --> v11  -Addressed Christoph's comments. We now have a  callback to struct iommu_resv_region to free all related memory and also dropped the FW specific union and now has a container struct iommu_iort_rmr_data. See patches #1 & #4 -Added R-by from Christoph. -Dropped R-by from Lorenzo for patches #4 & #5 due to the above changes. -Also dropped T-by from Steve and Laurentiu. Many thanks for your test efforts. I have done basic sanity testing on my platform but please do it again at your end. v9 --> v10 - Dropped patch #1 ("Add temporary RMR node flag definitions") since the ACPICA header updates patch is now in the mailing list - Based on the suggestion from Christoph, introduced a resv_region_free_fw_data() callback in struct iommu_resv_region and used that to free RMR specific memory allocations. v8 --> v9  - Adressed comments from Robin on interfaces.  - Addressed comments from Lorenzo. v7 --> v8   - Patch #1 has temp definitions for RMR related changes till     the ACPICA header changes are part of kernel.   - No early parsing of RMR node info and is only parsed at the     time of use.   - Changes to the RMR get/put API format compared to the     previous version.   - Support for RMR descriptor shared by multiple stream IDs. v6 --> v7  -fix pointed out by Steve to the SMMUv2 SMR bypass install in patch #8. v5 --> v6 - Addressed comments from Robin & Lorenzo.   : Moved iort_parse_rmr() to acpi_iort_init() from     iort_init_platform_devices().   : Removed use of struct iort_rmr_entry during the initial     parse. Using struct iommu_resv_region instead.   : Report RMR address alignment and overlap errors, but continue.   : Reworked arm_smmu_init_bypass_stes() (patch # 6). - Updated SMMUv2 bypass SMR code. Thanks to Jon N (patch #8). - Set IOMMU protection flags(IOMMU_CACHE, IOMMU_MMIO) based   on Type of RMR region. Suggested by Jon N. v4 --> v5  -Added a fw_data union to struct iommu_resv_region and removed   struct iommu_rmr (Based on comments from Joerg/Robin).  -Added iommu_put_rmrs() to release mem.  -Thanks to Steve for verifying on SMMUv2, but not added the Tested-by   yet because of the above changes. v3 -->v4 -Included the SMMUv2 SMR bypass install changes suggested by  Steve(patch #7) -As per Robin's comments, RMR reserve implementation is now  more generic  (patch #8) and dropped v3 patches 8 and 10. -Rebase to 5.13-rc1 RFC v2 --> v3  -Dropped RFC tag as the ACPICA header changes are now ready to be   part of 5.13[0]. But this series still has a dependency on that patch.  -Added IORT E.b related changes(node flags, _DSM function 5 checks for   PCIe).  -Changed RMR to stream id mapping from M:N to M:1 as per the spec and   discussion here[1].  -Last two patches add support for SMMUv2(Thanks to Jon Nettleton!) Jon Nettleton (1): iommu/arm-smmu: Get associated RMR info and install bypass SMR Shameer Kolothum (8): iommu: Introduce a callback to struct iommu_resv_region ACPI/IORT: Make iort_iommu_msi_get_resv_regions() return void ACPI/IORT: Provide a generic helper to retrieve reserve regions ACPI/IORT: Add support to retrieve IORT RMR reserved regions ACPI/IORT: Add a helper to retrieve RMR info directly iommu/arm-smmu-v3: Introduce strtab init helper iommu/arm-smmu-v3: Refactor arm_smmu_init_bypass_stes() to force bypass iommu/arm-smmu-v3: Get associated RMR info and install bypass STE drivers/acpi/arm64/iort.c | 360 ++++++++++++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 78 ++++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 52 +++ drivers/iommu/dma-iommu.c | 2 +- drivers/iommu/iommu.c | 16 +- include/linux/acpi_iort.h | 14 +- include/linux/iommu.h | 10 + 7 files changed, 486 insertions(+), 46 deletions(-) Tested-by: Laurentiu Tudor Tested-by: Hanjun Guo