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Sun, 15 May 2022 09:31:33 -0700 From: Besar Wicaksono To: , , , CC: , , , , , , , , , , Besar Wicaksono Subject: [PATCH v2 0/2] perf: ARM CoreSight PMU support Date: Sun, 15 May 2022 11:30:42 -0500 Message-ID: <20220515163044.50055-1-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220509002810.12412-1-bwicaksono@nvidia.com> References: <20220509002810.12412-1-bwicaksono@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 88d1a4ce-9363-4c15-5bd4-08da36906613 X-MS-TrafficTypeDiagnostic: MWHPR12MB1373:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ooiFPALhLq16GbPWZ3zPz9VfpQGi4ieetXJFvg7pVgLWUhPyiECncXZ+7xm8iz591nLP0zqq9lkHnHIdJUNKdsyJW5gGbx4wq1gt6KDlCddZK5+0DAl3yO72FMWFERucxy98TMndFp61yPg/yBNa74dwbnAgIqMm4dmiTJV4eFtYGvUFTI5w/CX5kSQJ0RL0ssm5gFGc3mW6vWhAZ0lihGWRJTsuf3j8KWf1MkqLb3zpKDMZtiPKcoldUdYUk1a0c/CTJtpbRELwqAr9ukQS/M/F0eaYI4G3mJWDQ0sU4du9BF3BvGkDhDvn/nRq2MABjbm81+MQnPjYQ4/1OoGtkI6vIKPdnnCRvJ0HOMzauDMCeE1kt9UPAcbVObN9u4L2KYJqXgn0MqiGK6eLZ2FQVKwinPi4flI0Jb3kYn9OQOnK73afgibxS1FfNI0zA+9z1vFSAm+LlkA87nitIbl7Y4OhOmihJFjJzbmmP4rfXMzJCzw+UV3kjBuAa/YMCjJNzdhZ7qQqrmNqLIbnB4EiKok042+Rl/Uz1DqFUtiCqkVEMfAofytJQHqhzkm6I0571D4vAHjnulso20KLPVMMz2ps70Nwn1aR47mvPaIkPudj77dNlx632pNxOp/h5xsPBdQmYPuQrgmiCGilQwLU4ZPKJqP4tUD0ALxh47JZrM+WJ6mMEbNWfXmlLjYh5dUOGOadg/j4kdF5j4549I/JgL6ivZSBPu+/nT1038ysMneqemIkAXq0srFoLMoBnzlsVqNpWZX3R9PTlhXyW2Emo/KY6rsziz5nr8X/rwonDbBcU7Rq+KDOlSyvxTh+SkS8Z7SVcTcAzn0l8CEbgthLAA== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(107886003)(4326008)(8676002)(81166007)(2616005)(2906002)(426003)(186003)(336012)(70206006)(70586007)(1076003)(82310400005)(36756003)(54906003)(36860700001)(966005)(508600001)(86362001)(7416002)(356005)(316002)(7696005)(40460700003)(83380400001)(6666004)(47076005)(110136005)(8936002)(26005)(5660300002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2022 16:31:44.0675 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 88d1a4ce-9363-4c15-5bd4-08da36906613 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1373 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220515_094633_709051_E5CC0FFA X-CRM114-Status: GOOD ( 12.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add driver support for ARM CoreSight PMU device and event attributes for NVIDIA implementation. The code is based on ARM Coresight PMU architecture and ACPI ARM Performance Monitoring Unit table (APMT) specification below: * ARM Coresight PMU: https://developer.arm.com/documentation/ihi0091/latest * APMT: https://developer.arm.com/documentation/den0117/latest Notes: * There is a concern on the naming of the PMU device. Currently the driver is probing "arm-coresight-pmu" device, however the APMT spec supports different kinds of CoreSight PMU based implementation. So it is open for discussion if the name can stay or a "generic" name is required. Please see the following thread: http://lists.infradead.org/pipermail/linux-arm-kernel/2022-May/740485.html Changes from v1: * Remove CPU arch dependency. * Remove 32-bit read/write helper function and just use read/writel. * Add .is_visible into event attribute to filter out cycle counter event. * Update pmiidr matching. * Remove read-modify-write on PMCR since the driver only writes to PMCR.E. * Assign default cycle event outside the 32-bit PMEVTYPER range. * Rework the active event and used counter tracking. Besar Wicaksono (2): perf: coresight_pmu: Add support for ARM CoreSight PMU driver perf: coresight_pmu: Add support for NVIDIA SCF and MCF attribute arch/arm64/configs/defconfig | 1 + drivers/perf/Kconfig | 2 + drivers/perf/Makefile | 1 + drivers/perf/coresight_pmu/Kconfig | 11 + drivers/perf/coresight_pmu/Makefile | 7 + .../perf/coresight_pmu/arm_coresight_pmu.c | 1271 +++++++++++++++++ .../perf/coresight_pmu/arm_coresight_pmu.h | 171 +++ .../coresight_pmu/arm_coresight_pmu_nvidia.c | 292 ++++ .../coresight_pmu/arm_coresight_pmu_nvidia.h | 17 + 9 files changed, 1773 insertions(+) create mode 100644 drivers/perf/coresight_pmu/Kconfig create mode 100644 drivers/perf/coresight_pmu/Makefile create mode 100644 drivers/perf/coresight_pmu/arm_coresight_pmu.c create mode 100644 drivers/perf/coresight_pmu/arm_coresight_pmu.h create mode 100644 drivers/perf/coresight_pmu/arm_coresight_pmu_nvidia.c create mode 100644 drivers/perf/coresight_pmu/arm_coresight_pmu_nvidia.h