From patchwork Mon May 16 00:54:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 12850176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23D50C433F5 for ; Mon, 16 May 2022 00:56:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=yF7n690pk3L/gCO5Le3jR7cftrQDYTa5DfsxAQ4Yf7Q=; b=z87BV/RnKz668g efzvuM939w9ONOePIWyQvqnXvRSkSCRfAxtbRvOKI8zhOA4dDTvfIbzuuWGn2Vh+t2StdGFvvNxJ7 Ntnbg7Z1UkEi0i9KquF3/oYuzj3koMr0YqzD1ipw/LSj1xwWivUSfy2XFTGM9vFE8QIsSeX+adMIs sp1nfQf1pzNeBZvQSTCCvBf+FrgTb2I8Y/GyyDgIN+HEzGWd5ilHGN/SPdcR0TQoQKEChus0nKYnv qGmUvQYVJhHU3qoEt4iD0jeY4+U4jsg3+BYKjrDTeqr7RaaSP20xIrm6nOfPpVkALnXVjJVScTyj1 cWXF0INSYYqTpr85z54w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqP1R-005RRy-Hx; Mon, 16 May 2022 00:55:41 +0000 Received: from twspam01.aspeedtech.com ([211.20.114.71]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqP0f-005Qxd-BJ for linux-arm-kernel@lists.infradead.org; Mon, 16 May 2022 00:54:57 +0000 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 24G0eWlr022581; Mon, 16 May 2022 08:40:32 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from Chiawei-PC03.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 16 May 2022 08:54:04 +0800 From: Chia-Wei Wang To: , , , , , , , , , , , CC: Subject: [PATCH v5 0/4] arm: aspeed: Add eSPI support Date: Mon, 16 May 2022 08:54:08 +0800 Message-ID: <20220516005412.4844-1-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 24G0eWlr022581 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220515_175453_697897_BAB194D9 X-CRM114-Status: GOOD ( 12.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch series add the driver support for the eSPI controller of Aspeed 5/6th generation SoCs. This controller is a slave device communicating with a master over Enhanced Serial Peripheral Interface (eSPI). It supports all of the 4 eSPI channels, namely peripheral, virtual wire, out-of-band, and flash, and operates at max frequency of 66MHz. v5: - unconditionally set VW GPIO to software mode as suggested by Jeremy - add missing DTS node for Aspeed G5 SoCs v4: - fix dt-bindgins error with patternProperties - fix data type warning for ARM64 compilation - replace header based implementation with .c files - add more description for the ioctl interface v3: - remove the redundant patch "clk: aspeed: Add eSPI reset bit" - fix missing header inclusion reported by test bot - fix dt-bindings error reported by yamllint v2: - remove irqchip implementation - merge per-channel drivers into single one to avoid the racing issue among eSPI handshake process and driver probing. Chia-Wei Wang (4): dt-bindings: aspeed: Add eSPI controller MAINTAINER: Add ASPEED eSPI driver entry soc: aspeed: Add eSPI driver ARM: dts: aspeed: Add eSPI node .../devicetree/bindings/soc/aspeed/espi.yaml | 162 +++++ MAINTAINERS | 9 + arch/arm/boot/dts/aspeed-g5.dtsi | 17 + arch/arm/boot/dts/aspeed-g6.dtsi | 17 + drivers/soc/aspeed/Kconfig | 11 + drivers/soc/aspeed/Makefile | 5 + drivers/soc/aspeed/aspeed-espi-ctrl.c | 214 +++++++ drivers/soc/aspeed/aspeed-espi-ctrl.h | 309 ++++++++++ drivers/soc/aspeed/aspeed-espi-flash.c | 352 +++++++++++ drivers/soc/aspeed/aspeed-espi-flash.h | 45 ++ drivers/soc/aspeed/aspeed-espi-ioc.h | 195 ++++++ drivers/soc/aspeed/aspeed-espi-oob.c | 558 ++++++++++++++++++ drivers/soc/aspeed/aspeed-espi-oob.h | 70 +++ drivers/soc/aspeed/aspeed-espi-perif.c | 511 ++++++++++++++++ drivers/soc/aspeed/aspeed-espi-perif.h | 45 ++ drivers/soc/aspeed/aspeed-espi-vw.c | 142 +++++ drivers/soc/aspeed/aspeed-espi-vw.h | 21 + 17 files changed, 2683 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/espi.yaml create mode 100644 drivers/soc/aspeed/aspeed-espi-ctrl.c create mode 100644 drivers/soc/aspeed/aspeed-espi-ctrl.h create mode 100644 drivers/soc/aspeed/aspeed-espi-flash.c create mode 100644 drivers/soc/aspeed/aspeed-espi-flash.h create mode 100644 drivers/soc/aspeed/aspeed-espi-ioc.h create mode 100644 drivers/soc/aspeed/aspeed-espi-oob.c create mode 100644 drivers/soc/aspeed/aspeed-espi-oob.h create mode 100644 drivers/soc/aspeed/aspeed-espi-perif.c create mode 100644 drivers/soc/aspeed/aspeed-espi-perif.h create mode 100644 drivers/soc/aspeed/aspeed-espi-vw.c create mode 100644 drivers/soc/aspeed/aspeed-espi-vw.h