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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id y12-20020a5d620c000000b0021d63fe0f03sm1626730wru.12.2022.07.09.08.24.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jul 2022 08:24:38 -0700 (PDT) From: Conor Dooley To: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J . Wysocki" Cc: Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld , Guo Ren , Anup Patel , Atish Patra , Heiko Stuebner , Philipp Tomsich , Rob Herring , Marc Zyngier , Viresh Kumar , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Brice Goglin Subject: [PATCH v3 0/2] Fix RISC-V's arch-topology reporting Date: Sat, 9 Jul 2022 16:23:53 +0100 Message-Id: <20220709152354.2856586-1-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220709_082444_601222_0BEB6CBC X-CRM114-Status: GOOD ( 17.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Conor Dooley Hey all, It's my first time messing around with arch/ code at all, let alone more than one arch, so forgive me if I have screwed up how to do a migration like this. The goal here is the fix the incorrectly reported arch topology on RISC-V which seems to have been broken since it was added. cpu, package and thread IDs are all currently reported as -1, so tools like lstopo think systems have multiple threads on the same core when this is not true: https://github.com/open-mpi/hwloc/issues/536 arm64's topology code basically applies to RISC-V too, so it has been made generic along with the removal of MPIDR related code, which appears to be redudant code since '3102bc0e6ac7 ("arm64: topology: Stop using MPIDR for topology information")' replaced the code that actually interacted with MPIDR with default values. I only built tested for arm{,64} , so hopefully it is not broken when used. Testing on both arm64 & !SMP RISC-V would really be appreciated! For V2, I dropped the idea of doing a RISC-V specific implementation followed by a move to the generic code & just went for the more straight forward method of moving to the shared version first. I also dropped the RFC. V3 moves store_cpu_topology() down inside the arch check alongside the init function so that boot on 32bit arm is not broken. Thanks, Conor Conor Dooley (2): arm64: topology: move store_cpu_topology() to shared code riscv: topology: fix default topology reporting arch/arm64/kernel/topology.c | 40 ------------------------------------ arch/riscv/Kconfig | 2 +- arch/riscv/kernel/smpboot.c | 4 +++- drivers/base/arch_topology.c | 19 +++++++++++++++++ 4 files changed, 23 insertions(+), 42 deletions(-) base-commit: b6f1f2fa2bddd69ff46a190b8120bd440fd50563