From patchwork Fri Sep 9 16:59:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 12971991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00831C6FA8E for ; Fri, 9 Sep 2022 17:01:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=eYDG3BypK1/giaQ8IYoqyD20kdTlKbQP5jrIzKC941g=; b=uvwYfrOUWfe+Lb znFrzkelELqf+/0BanTx0+tmfuogVHSyulZBnNiOQ367Yl8CzvIRVT+GzjgfR8A3xCBztBZyg4xic GuMtXXg1z6thLXfrYD2wFHu2X20+wymvxjZeye4qtXP92LvDr2Au+BdOXH6R2Uk9JwCIMTrXGk4j9 wQguixoyPzYgGNVnQovwKIYdqklDS59AkzHsx4Uf7iajcDJ698GySfFgiQ7mwFwLvTZR50fpV+Cg/ twWHzLL7Qgz0TSBh/PbPozsXY5UNYR7L8LmelSJwk8fCmGGXpY9vdLlwkrF3jNdmiAGMUwXSgzPmX lu/8733wksO9FCF4MawQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWhME-000WqA-GM; Fri, 09 Sep 2022 16:59:58 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWhMB-000Wnc-9n for linux-arm-kernel@lists.infradead.org; Fri, 09 Sep 2022 16:59:57 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DB113165C; Fri, 9 Sep 2022 09:59:57 -0700 (PDT) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.197.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C3CDA3F73D; Fri, 9 Sep 2022 09:59:50 -0700 (PDT) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Suzuki K Poulose , Will Deacon , James Morse Subject: [PATCH 0/3] arm64: errata: remove BF16 HWCAP due to incorrect result on Cortex-A510 Date: Fri, 9 Sep 2022 17:59:35 +0100 Message-Id: <20220909165938.3931307-1-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220909_095955_406276_1F3192AB X-CRM114-Status: GOOD ( 12.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello! Cortex-A510 has an erratum where the BFMMLA or VMMLA instructions might produce the incorrect result. This only happens if two Cortex-A510 CPUs are configured by the SoC manafacturer in a particular way to share some hardware, and are using it at the same time. It isn't possible for linux to know how the CPUs were configured, so the only option is to disable the BF16 feature for all Cortex-A510 CPUs. This won't stop user-space from trying to use the instructions to see if they work - but such software is already broken on big/little systems with mismathed features. Removing the BF16 feature involves removing both the HWCAP, as was done by commit 44b3834b2eed "arm64: errata: Remove AES hwcap for COMPAT tasks", and the emulated view of that register that user-space has. (This wasn't previously needed as aarch32 ID registers aren't accessible like this). As there are now two of these things, this series tries to add a more maintainable way to remove features, to avoid spilling workaround like this into cpufeature.c. Instead, cpu_errata.c modifies the user_mask that is used for emulation of the id registers, and cpufeature.c builds the HWCAPs based on this. I have patches to convert the AES workaround to do the same, but that should wait until the aarch32 ID registers are generated by the sysreg awk scripts (it needs some new masks defined). [0] https://developer.arm.com/documentation/SDEN1873351/1400/?lang=en Thanks, James Morse (3): arm64: cpufeature: Force HWCAP to be based on the sysreg visible to user-space arm64: cpufeature: Expose get_arm64_ftr_reg() outside cpufeature.c arm64: errata: remove BF16 HWCAP due to incorrect result on Cortex-A510 Documentation/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 14 +++++++++ arch/arm64/include/asm/cpufeature.h | 2 ++ arch/arm64/kernel/cpu_errata.c | 27 ++++++++++++++++ arch/arm64/kernel/cpufeature.c | 43 ++++++++++++++++++++------ arch/arm64/tools/cpucaps | 1 + 6 files changed, 79 insertions(+), 10 deletions(-)