From patchwork Mon Sep 26 17:55:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 12989187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9E8AC6FA82 for ; Mon, 26 Sep 2022 17:57:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=s3H9WXGwx4uVuleXFu6E64lfQDZhptCVZ9HSMEHvt40=; b=4FmcaKQfXpZX9W i2aZs2WJguumiAWPlABV8orqXjP9PAjs9dmmWXMI4LRIOXme23yBdACeLvqCK/RaPmENvYq/xCYXd UwVDSuwpqoVEh/xFGIojUYYBH6cnS0u4aYtm1fAvx/dpLy2DeMrWl+7zHCG8DWHqjikiJ3MzJ7njA uNUPE0Eygh8sYvSCubBxEmqXGHcOaZtlG5gnwC1JC1NTUYekFctZ0q/Fyo1dBQvx1KizM8slLTsgM UyvfCvVkVDesTbIM+LoFnOC5TLMRVkBZwuJSkMJuISeF90ErDBMhOERBSxIZxR+WcJ+acoOQWqCdO TKAE9w/oJHvO9isAzItQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocsKl-006ATG-JU; Mon, 26 Sep 2022 17:55:59 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocsKj-006AR3-0K for linux-arm-kernel@lists.infradead.org; Mon, 26 Sep 2022 17:55:58 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28QHthQf097060; Mon, 26 Sep 2022 12:55:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1664214943; bh=UdR3bIkAnTA+v1r1BDJ+WSGiuxRccrB018S2Y/swOvw=; h=From:To:CC:Subject:Date; b=i34E6avv0ThKMGu1u9f7gZtDGOvGux7jg8ulaYMnblaiQ1OGiz9AqvizLbeVobmXP of2/u2A3WXhwE7ZBCnisc4n6VN7UIsFXSf8wx2iuqGFn7WKdpu5JRJ8cTy488pgJPX w6A0SqwVTtqQsDEwghaSeiLmjAgua6ywO6xVUDyU= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28QHthKP017316 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 26 Sep 2022 12:55:43 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Mon, 26 Sep 2022 12:55:43 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Mon, 26 Sep 2022 12:55:43 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 28QHteWW037317; Mon, 26 Sep 2022 12:55:42 -0500 From: Matt Ranostay To: , , , , CC: , , , Matt Ranostay Subject: [PATCH v2 0/3] PCI: add 4x lane support for pci-j721e controllers Date: Mon, 26 Sep 2022 10:55:35 -0700 Message-ID: <20220926175538.362018-1-mranostay@ti.com> X-Mailer: git-send-email 2.38.0.rc0.52.gdda7228a83 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220926_105557_180096_ADFF4860 X-CRM114-Status: UNSURE ( 8.30 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adding of dditional support to Cadence PCIe controller (i.e. pci-j721e.c) for up to 4x lanes, and reworking of driver to define maximum lanes per board configuration. Changes from v1: * Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause regressions on 1-2x lane platforms Matt Ranostay (3): PCI: j721e: Add PCIe 4x lane selection support PCI: j721e: Add per platform maximum lane settings PCI: j721e: Add warnings on num-lanes misconfiguration drivers/pci/controller/cadence/pci-j721e.c | 27 ++++++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-)