From patchwork Thu Nov 10 01:42:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 13038212 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8DF0C4332F for ; Thu, 10 Nov 2022 01:45:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=YXsTBOCHW4Kcx6d+Ck+0S8rknO/epqyhjIKtZkC2+ds=; b=Y550RtP00WMbvc /MhA9F0kHhn2hMjGxRs0eARrpfMiVz0nilNy8wOmqyVch/Uxm4DnsqIZ54qctT8+dZ4wdvuru4fAF VDr2LQzs1illUsa6Qg1HvI+ZvAIUGuabc3m55w3Zx859udp8dhInsYtXVv9rylFsydVlWTv3npj3v qNjQoh+veQAjHZgSEjqGpXuk2TEOQ3vVI/fsBsqIw12O7cF28Li0svvdk3lCBiC0kfr496/3K8nQJ gAolGY6c+M1FyssCZ5KLnZ8NuTaGFSIEQzMoizBuSll3iKhzWQC4o0MoNc1XkbM1uTE1+htQcOy0b 6oqBezoZD+SJEpPrtlpg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oswcG-001hwz-2p; Thu, 10 Nov 2022 01:44:28 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oswcD-001hw7-6C for linux-arm-kernel@lists.infradead.org; Thu, 10 Nov 2022 01:44:26 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E8B671FB; Wed, 9 Nov 2022 17:44:27 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3AF633F703; Wed, 9 Nov 2022 17:44:20 -0800 (PST) From: Andre Przywara To: Linus Walleij , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Icenowy Zheng , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [RFC PATCH 0/2] pinctrl: sunxi: Introduce DT-based pinctrl builder Date: Thu, 10 Nov 2022 01:42:53 +0000 Message-Id: <20221110014255.20711-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.5 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221109_174425_290051_425271C6 X-CRM114-Status: GOOD ( 14.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, since the dawn of time every Allwinner SoC dumped a rather large table of data into the kernel, to describe the mapping between the pinctrl function name and its mux value, for each pin. This series introduces code that avoids that (for new SoCs), by instead reading that information directly from the devicetree. We have per-pin group nodes there anyway, and were just missing the mux value. Compared to my previous effort almost exactly five years ago [1], this new version drops the idea of describing the pinctrl data entirely in the DT, instead it still relies on driver provided information for that. That is more flexible, since it allows to introduce quirks and special handling more cleanly, at the cost of still requiring a separate driver file for each SoC. However this file is now very small, and can be easily written and reviewed. All that is needed is the number of pins per bank, plus information about each bank's IRQ capability. Patch 2/2 shows an example, for the yet unsupported Allwinner V5 SoC. On the DT side all that would be needed is *one* extra property per pin group to announce the mux value: uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; function = "uart0"; pinmux = <2>; }; The new code works by providing a function that builds the former mapping table *at runtime*, by using both the driver provided information, plus traversing all children of the pinctrl DT node, to find all pin groups needed. This table looks the same as what we hardcoded so far, so can easily be digested by the existing sunxi pinctrl driver. Please have a look and tell me whether this new approach has a better future than my previous attempt. Cheers, Andre [1] https://patchwork.ozlabs.org/project/linux-gpio/cover/20171113012523.2328-1-andre.przywara@arm.com/ Andre Przywara (2): pinctrl: sunxi: allow reading mux values from DT pinctrl: sunxi: Add support for the Allwinner V5 pin controller drivers/pinctrl/sunxi/Kconfig | 5 + drivers/pinctrl/sunxi/Makefile | 2 + drivers/pinctrl/sunxi/pinctrl-sun8i-v5.c | 52 ++++ drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c | 355 +++++++++++++++++++++++ drivers/pinctrl/sunxi/pinctrl-sunxi.h | 8 + 5 files changed, 422 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v5.c create mode 100644 drivers/pinctrl/sunxi/pinctrl-sunxi-dt.c