mbox series

[V2,0/9] Add minimal boot support for IPQ5332

Message ID 20230130114702.20606-1-quic_kathirav@quicinc.com (mailing list archive)
Headers show
Series Add minimal boot support for IPQ5332 | expand

Message

Kathiravan Thirumoorthy Jan. 30, 2023, 11:46 a.m. UTC 
From: Kathiravan T <quic_kathirav@quicinc.com>

The IPQ5332 is Qualcomm's 802.11ax SoC for Routers, Gateways and
Access Points.

This series adds minimal board boot support for ipq5332-mi01.2 board.

Also, this series depends on the below patch
https://lore.kernel.org/linux-arm-msm/20230120082631.22053-1-quic_kathirav@quicinc.com/

Changes in V2:
	- Rebased on linux-next/master
	- Dropped the 'dt-bindings: mmc: sdhci-msm: add IPQ5332 compatible',
	  since it is already part of linux-next/master
	- Added a new patch 'clk: qcom: ipq5332: mark GPLL4 as critical temporarily'
	- Detailed change log is present in respective patches
	- V1 can be found at
	  https://lore.kernel.org/linux-arm-msm/20230125104520.89684-1-quic_kathirav@quicinc.com/

Kathiravan T (9):
  dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
  pinctrl: qcom: Introduce IPQ5332 TLMM driver
  clk: qcom: Add STROMER PLUS PLL type for IPQ5332
  dt-bindings: clock: Add Qualcomm IPQ5332 GCC
  clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
  dt-bindings: qcom: add ipq5332 boards
  dt-bindings: firmware: qcom,scm: document IPQ5332 SCM
  arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support
  arm64: defconfig: Enable IPQ5332 SoC base configs

 .../devicetree/bindings/arm/qcom.yaml         |    7 +
 .../bindings/clock/qcom,ipq5332-gcc.yaml      |   61 +
 .../bindings/firmware/qcom,scm.yaml           |    1 +
 .../bindings/pinctrl/qcom,ipq5332-tlmm.yaml   |  136 +
 arch/arm64/boot/dts/qcom/Makefile             |    1 +
 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts   |   71 +
 arch/arm64/boot/dts/qcom/ipq5332.dtsi         |  272 ++
 arch/arm64/configs/defconfig                  |    2 +
 drivers/clk/qcom/Kconfig                      |    8 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/clk-alpha-pll.c              |   11 +
 drivers/clk/qcom/clk-alpha-pll.h              |    1 +
 drivers/clk/qcom/gcc-ipq5332.c                | 3954 +++++++++++++++++
 drivers/pinctrl/qcom/Kconfig                  |   10 +
 drivers/pinctrl/qcom/Makefile                 |    1 +
 drivers/pinctrl/qcom/pinctrl-ipq5332.c        | 1008 +++++
 include/dt-bindings/clock/qcom,ipq5332-gcc.h  |  359 ++
 17 files changed, 5904 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
 create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
 create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi
 create mode 100644 drivers/clk/qcom/gcc-ipq5332.c
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5332.c
 create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h

Comments

Krzysztof Kozlowski Jan. 31, 2023, 7:27 p.m. UTC | #1 
On 30/01/2023 12:46, Kathiravan Thirumoorthy wrote:
> From: Kathiravan T <quic_kathirav@quicinc.com>
> 
> The IPQ5332 is Qualcomm's 802.11ax SoC for Routers, Gateways and
> Access Points.
> 
> This series adds minimal board boot support for ipq5332-mi01.2 board.
> 
> Also, this series depends on the below patch
> https://lore.kernel.org/linux-arm-msm/20230120082631.22053-1-quic_kathirav@quicinc.com/

You sent it even before answering to me in old thread, so even before
giving me a chance to read your answer... Don't send v2 before we finish
discussing previous one.

Best regards,
Krzysztof
Stephen Boyd Jan. 31, 2023, 9:09 p.m. UTC | #2 
Quoting Kathiravan Thirumoorthy (2023-01-30 03:46:58)
> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
> new file mode 100644
> index 000000000000..a8ce618bb81b
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-ipq5332.c
> @@ -0,0 +1,3954 @@
[...]
> +
> +static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
> +
> +static struct clk_alpha_pll gpll0_main = {
[...]
> +};
> +
> +static const struct parent_map gcc_parent_map_3[] = {
> +       { P_XO, 0 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_3[] = {

Isn't this the same as gcc_parent_data_xo?

> +       { .index = DT_XO },
> +};
> +
> +static const struct parent_map gcc_parent_map_4[] = {
> +       { P_XO, 0 },
> +       { P_GPLL0_OUT_MAIN, 1 },
> +       { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
> +       { P_SLEEP_CLK, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_4[] = {
> +       { .index = DT_XO },
> +       { .hw = &gpll0.clkr.hw },
> +       { .hw = &gpll0_div2.hw },
[..]
> +
> +static int gcc_ipq5332_probe(struct platform_device *pdev)
> +{
> +       struct regmap *regmap;
> +
> +       regmap = qcom_cc_map(pdev, &gcc_ipq5332_desc);
> +       if (IS_ERR(regmap))
> +               return PTR_ERR(regmap);
> +
> +       return qcom_cc_really_probe(pdev, &gcc_ipq5332_desc, regmap);

If you don't need to write anything in probe you can simply use
qcom_cc_probe().
Kathiravan Thirumoorthy Feb. 1, 2023, 5:43 a.m. UTC | #3 
On 2/1/2023 12:57 AM, Krzysztof Kozlowski wrote:
> On 30/01/2023 12:46, Kathiravan Thirumoorthy wrote:
>> From: Kathiravan T <quic_kathirav@quicinc.com>
>>
>> The IPQ5332 is Qualcomm's 802.11ax SoC for Routers, Gateways and
>> Access Points.
>>
>> This series adds minimal board boot support for ipq5332-mi01.2 board.
>>
>> Also, this series depends on the below patch
>> https://lore.kernel.org/linux-arm-msm/20230120082631.22053-1-quic_kathirav@quicinc.com/
> You sent it even before answering to me in old thread, so even before
> giving me a chance to read your answer... Don't send v2 before we finish
> discussing previous one.


Got it, I have responded to your queries in V2. I will wait for couple 
of days to see if any other comments are coming in.


>
> Best regards,
> Krzysztof
>
Kathiravan Thirumoorthy Feb. 1, 2023, 5:45 a.m. UTC | #4 
On 2/1/2023 2:39 AM, Stephen Boyd wrote:
> Quoting Kathiravan Thirumoorthy (2023-01-30 03:46:58)
>> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
>> new file mode 100644
>> index 000000000000..a8ce618bb81b
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-ipq5332.c
>> @@ -0,0 +1,3954 @@
> [...]
>> +
>> +static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
>> +
>> +static struct clk_alpha_pll gpll0_main = {
> [...]
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_3[] = {
>> +       { P_XO, 0 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_3[] = {
> Isn't this the same as gcc_parent_data_xo?
>
>> +       { .index = DT_XO },
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_4[] = {
>> +       { P_XO, 0 },
>> +       { P_GPLL0_OUT_MAIN, 1 },
>> +       { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
>> +       { P_SLEEP_CLK, 6 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_4[] = {
>> +       { .index = DT_XO },
>> +       { .hw = &gpll0.clkr.hw },
>> +       { .hw = &gpll0_div2.hw },
> [..]
>> +
>> +static int gcc_ipq5332_probe(struct platform_device *pdev)
>> +{
>> +       struct regmap *regmap;
>> +
>> +       regmap = qcom_cc_map(pdev, &gcc_ipq5332_desc);
>> +       if (IS_ERR(regmap))
>> +               return PTR_ERR(regmap);
>> +
>> +       return qcom_cc_really_probe(pdev, &gcc_ipq5332_desc, regmap);
> If you don't need to write anything in probe you can simply use
> qcom_cc_probe().


Thanks Stephen, will move to qcom_cc_probe in V3.
Kathiravan Thirumoorthy Feb. 1, 2023, 5:46 a.m. UTC | #5 
On 2/1/2023 11:15 AM, Kathiravan T wrote:
>
> On 2/1/2023 2:39 AM, Stephen Boyd wrote:
>> Quoting Kathiravan Thirumoorthy (2023-01-30 03:46:58)
>>> diff --git a/drivers/clk/qcom/gcc-ipq5332.c 
>>> b/drivers/clk/qcom/gcc-ipq5332.c
>>> new file mode 100644
>>> index 000000000000..a8ce618bb81b
>>> --- /dev/null
>>> +++ b/drivers/clk/qcom/gcc-ipq5332.c
>>> @@ -0,0 +1,3954 @@
>> [...]
>>> +
>>> +static const struct clk_parent_data gcc_parent_data_xo = { .index = 
>>> DT_XO };
>>> +
>>> +static struct clk_alpha_pll gpll0_main = {
>> [...]
>>> +};
>>> +
>>> +static const struct parent_map gcc_parent_map_3[] = {
>>> +       { P_XO, 0 },
>>> +};
>>> +
>>> +static const struct clk_parent_data gcc_parent_data_3[] = {
>> Isn't this the same as gcc_parent_data_xo?


Sorry missed in previous reply. Yeah correct. Will remove it and also 
check if any further duplicate entries.


>>
>>> +       { .index = DT_XO },
>>> +};
>>> +
>>> +static const struct parent_map gcc_parent_map_4[] = {
>>> +       { P_XO, 0 },
>>> +       { P_GPLL0_OUT_MAIN, 1 },
>>> +       { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
>>> +       { P_SLEEP_CLK, 6 },
>>> +};
>>> +
>>> +static const struct clk_parent_data gcc_parent_data_4[] = {
>>> +       { .index = DT_XO },
>>> +       { .hw = &gpll0.clkr.hw },
>>> +       { .hw = &gpll0_div2.hw },
>> [..]
>>> +
>>> +static int gcc_ipq5332_probe(struct platform_device *pdev)
>>> +{
>>> +       struct regmap *regmap;
>>> +
>>> +       regmap = qcom_cc_map(pdev, &gcc_ipq5332_desc);
>>> +       if (IS_ERR(regmap))
>>> +               return PTR_ERR(regmap);
>>> +
>>> +       return qcom_cc_really_probe(pdev, &gcc_ipq5332_desc, regmap);
>> If you don't need to write anything in probe you can simply use
>> qcom_cc_probe().
>
>
> Thanks Stephen, will move to qcom_cc_probe in V3.
>
>