From patchwork Thu Feb 16 18:21:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13143658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C82BC636CC for ; Thu, 16 Feb 2023 18:23:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=81POml7ge6jNsQ0Pv9HmqIDssRYlk8aFEOgMQ8jNK1g=; b=qn9eFnDZMO6b7Q dMHcQd0iy2245EeA0qDInJvZpFlPUI4A+JqdCK6Tt/HtmRRg8idLui5DakKjR6u/sLGBginv8KixL zMLktFHivyzDtVlq/gwsXVIyFuNfv5a4qjUkOnChLVh77AtPdjW2poE+afJaL9Re/aq+pBIrHPtNg 6O89nKn7YaOvT/lOrRVC6iYtsXss0FFzm43ERMveMJDvVZ4UxFF6ALoiiMn1KdkukuWyF+K4JHrCp GrSxjOPG8Glmv2fPo65R064xZnVqgAYyd3p1ly1/Afe/2+lIVCe+Vaj18S+VjMbjcoOhYcCsKegQP Rx0HZa4CyPR/ozVMDZDQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pSits-00BUTz-Lf; Thu, 16 Feb 2023 18:22:34 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pSitj-00BUIk-38 for linux-arm-kernel@lists.infradead.org; Thu, 16 Feb 2023 18:22:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2BA4C1042; Thu, 16 Feb 2023 10:22:59 -0800 (PST) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3E1513F663; Thu, 16 Feb 2023 10:22:15 -0800 (PST) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , Marc Zyngier , Oliver Upton , James Morse Subject: [RFC PATCH 0/3] arm64: errata: Disable FWB on parts with non-ARM interconnects Date: Thu, 16 Feb 2023 18:21:58 +0000 Message-Id: <20230216182201.1705406-1-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230216_102223_260744_A0740CD0 X-CRM114-Status: GOOD ( 15.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello! When stage1 translation is disabled, the SCTRL_E1.I bit controls the attributes used for instruction fetch, one of the options results in a non-cacheable access. A whole host of CPUs missed the FWB override in this case, meaning a KVM guest could fetch stale/junk data instead of instructions. The workaround is to disable FWB, and do the required cache maintenance instead. The good news is, this isn't a problem for systems using Arm's interconnect IP. The bad news is: linux can't know this. Arm knows of at least one platform that is affected by this erratum. This series adds support for the 'Errata Management Firmware Interface', [0] and queries that to determine if the CPU is affected or not. Unfortunately, no-one has firmware that supports this new interface yet, and the least surprising thing to do is to enable the workaround by default, meaning FWB is disabled on all these cores, even for unaffected platforms. Platforms that are not-affected can either take a firmware-update to support the interface, or if the kernel they run will only run on hardware that is unaffected, disable the workaround at build time. The trusted firmware series to implement the interface has not yet been posted. I'll include a link once it is. This series is an RFC as I anticipate a wider discussion around how we add workaround that depend on firmware for detection. The SDEN documents that describe this are: Cortex-A78: https://developer.arm.com/documentation/SDEN1401784/1800/?lang=en Cortex-A78C: https://developer.arm.com/documentation/SDEN1707916/1300/?lang=en https://developer.arm.com/documentation/SDEN2004089/0700/?lang=en (yes, there are two!) Cortex-A710: https://developer.arm.com/documentation/SDEN1775101/1500/?lang=en Cortex-X1: https://developer.arm.com/documentation/SDEN1401782/1800/?lang=en Cortex-X2: https://developer.arm.com/documentation/SDEN1775100/1500/?lang=en Cortex-X3: https://developer.arm.com/documentation/SDEN2055130/1000/?lang=en Cortex-V1: https://developer.arm.com/documentation/SDEN1401781/1600/?lang=en Cortex-V2: https://developer.arm.com/documentation/SDEN2332927/0500/?lang=en Cortex-N2: https://developer.arm.com/documentation/SDEN1982442/1200/?lang=en Thanks, James [0] https://developer.arm.com/documentation/den0100/1-0/?lang=en James Morse (3): firmware: smccc: Add support for erratum discovery API arm64: cputype: Add new part numbers for Cortex-X3, and Neoverse-V2 arm64: errata: Disable FWB on parts with non-ARM interconnects Documentation/arm64/silicon-errata.rst | 18 ++++++ arch/arm64/Kconfig | 27 +++++++++ arch/arm64/include/asm/cputype.h | 4 ++ arch/arm64/kernel/cpufeature.c | 77 ++++++++++++++++++++++++- drivers/firmware/smccc/Kconfig | 8 +++ drivers/firmware/smccc/Makefile | 1 + drivers/firmware/smccc/em.c | 78 ++++++++++++++++++++++++++ include/linux/arm-smccc.h | 28 +++++++++ 8 files changed, 240 insertions(+), 1 deletion(-) create mode 100644 drivers/firmware/smccc/em.c