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[v2,0/6] clk: samsung: exynos850: Add missing clocks for PM

Message ID 20230223042133.26551-1-semen.protsenko@linaro.org (mailing list archive)
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Series clk: samsung: exynos850: Add missing clocks for PM | expand

Message

Sam Protsenko Feb. 23, 2023, 4:21 a.m. UTC 
As a part of preparation for PM enablement in Exynos850 clock driver,
this patch series implements CMU_G3D, and also main gate clocks for AUD
and HSI CMUs. The series brings corresponding changes to bindings, the
driver and SoC dts file.

Changes in v2:
  - Rebased all patches on top of the most recent soc/for-next tree
  - Added A-b and R-b tags
  - Minor fixes

Sam Protsenko (6):
  dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
  dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
  clk: samsung: clk-pll: Implement pll0818x PLL type
  clk: samsung: exynos850: Implement CMU_G3D domain
  clk: samsung: exynos850: Add AUD and HSI main gate clocks
  arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC

 .../clock/samsung,exynos850-clock.yaml        |  19 +++
 arch/arm64/boot/dts/exynos/exynos850.dtsi     |   9 ++
 drivers/clk/samsung/clk-exynos850.c           | 139 ++++++++++++++++++
 drivers/clk/samsung/clk-pll.c                 |   1 +
 drivers/clk/samsung/clk-pll.h                 |   1 +
 include/dt-bindings/clock/exynos850.h         |  28 +++-
 6 files changed, 194 insertions(+), 3 deletions(-)

Comments

Krzysztof Kozlowski March 6, 2023, 2:28 p.m. UTC | #1 
On Wed, 22 Feb 2023 22:21:27 -0600, Sam Protsenko wrote:
> As a part of preparation for PM enablement in Exynos850 clock driver,
> this patch series implements CMU_G3D, and also main gate clocks for AUD
> and HSI CMUs. The series brings corresponding changes to bindings, the
> driver and SoC dts file.
> 
> Changes in v2:
>   - Rebased all patches on top of the most recent soc/for-next tree
>   - Added A-b and R-b tags
>   - Minor fixes
> 
> [...]

Applied, thanks!

[1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
      https://git.kernel.org/krzk/linux/c/067ba1605806e52118bb598afb357718df9f0e19
[2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
      https://git.kernel.org/krzk/linux/c/e289665ed0d6df9fca3ebc128f1232d305e4600b
[3/6] clk: samsung: clk-pll: Implement pll0818x PLL type
      https://git.kernel.org/krzk/linux/c/a6feedab8ab9a9e4483deb0bcc87919d92c88b7e
[4/6] clk: samsung: exynos850: Implement CMU_G3D domain
      https://git.kernel.org/krzk/linux/c/c5704a56893b4e77e434597c7c53d878bb3073b0
[5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks
      https://git.kernel.org/krzk/linux/c/d8d12e0d079aff4b1d8079a0a55944c0596f1d67
[6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC
      https://git.kernel.org/krzk/linux/c/ad8f6ad9a4f219950df65731a8ff91baa022c4b0

Best regards,
Krzysztof Kozlowski March 6, 2023, 3:51 p.m. UTC | #2 
On 06/03/2023 15:28, Krzysztof Kozlowski wrote:
> On Wed, 22 Feb 2023 22:21:27 -0600, Sam Protsenko wrote:
>> As a part of preparation for PM enablement in Exynos850 clock driver,
>> this patch series implements CMU_G3D, and also main gate clocks for AUD
>> and HSI CMUs. The series brings corresponding changes to bindings, the
>> driver and SoC dts file.
>>
>> Changes in v2:
>>   - Rebased all patches on top of the most recent soc/for-next tree
>>   - Added A-b and R-b tags
>>   - Minor fixes
>>
>> [...]
> 
> Applied, thanks!
> 
> [1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
>       https://git.kernel.org/krzk/linux/c/067ba1605806e52118bb598afb357718df9f0e19
> [2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
>       https://git.kernel.org/krzk/linux/c/e289665ed0d6df9fca3ebc128f1232d305e4600b
> [3/6] clk: samsung: clk-pll: Implement pll0818x PLL type
>       https://git.kernel.org/krzk/linux/c/a6feedab8ab9a9e4483deb0bcc87919d92c88b7e
> [4/6] clk: samsung: exynos850: Implement CMU_G3D domain
>       https://git.kernel.org/krzk/linux/c/c5704a56893b4e77e434597c7c53d878bb3073b0
> [5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks
>       https://git.kernel.org/krzk/linux/c/d8d12e0d079aff4b1d8079a0a55944c0596f1d67
> [6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC
>       https://git.kernel.org/krzk/linux/c/ad8f6ad9a4f219950df65731a8ff91baa022c4b0

And builds are broken. Please mention in cover letter or commit
dependencies and ordering...

Best regards,
Krzysztof
Sam Protsenko March 6, 2023, 6:55 p.m. UTC | #3 
On Mon, 6 Mar 2023 at 09:51, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 06/03/2023 15:28, Krzysztof Kozlowski wrote:
> > On Wed, 22 Feb 2023 22:21:27 -0600, Sam Protsenko wrote:
> >> As a part of preparation for PM enablement in Exynos850 clock driver,
> >> this patch series implements CMU_G3D, and also main gate clocks for AUD
> >> and HSI CMUs. The series brings corresponding changes to bindings, the
> >> driver and SoC dts file.
> >>
> >> Changes in v2:
> >>   - Rebased all patches on top of the most recent soc/for-next tree
> >>   - Added A-b and R-b tags
> >>   - Minor fixes
> >>
> >> [...]
> >
> > Applied, thanks!
> >
> > [1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
> >       https://git.kernel.org/krzk/linux/c/067ba1605806e52118bb598afb357718df9f0e19
> > [2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
> >       https://git.kernel.org/krzk/linux/c/e289665ed0d6df9fca3ebc128f1232d305e4600b
> > [3/6] clk: samsung: clk-pll: Implement pll0818x PLL type
> >       https://git.kernel.org/krzk/linux/c/a6feedab8ab9a9e4483deb0bcc87919d92c88b7e
> > [4/6] clk: samsung: exynos850: Implement CMU_G3D domain
> >       https://git.kernel.org/krzk/linux/c/c5704a56893b4e77e434597c7c53d878bb3073b0
> > [5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks
> >       https://git.kernel.org/krzk/linux/c/d8d12e0d079aff4b1d8079a0a55944c0596f1d67
> > [6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC
> >       https://git.kernel.org/krzk/linux/c/ad8f6ad9a4f219950df65731a8ff91baa022c4b0
>
> And builds are broken. Please mention in cover letter or commit
> dependencies and ordering...
>

Just checked all most recent commits on your for-next and next/clk
branches. Seem to build fine for me. AFAIR I checked all patches in
that series, and I guess there shouldn't be any issues if you apply
those in the same order they are numbered inside the series. Or you
mean you have some clash between different series? Anyways, I'm glad
to help, but I'd need more details on where exactly the problem is (or
maybe you already fixed it?).

Thanks!

> Best regards,
> Krzysztof
>
Krzysztof Kozlowski March 7, 2023, 7:47 a.m. UTC | #4 
On 06/03/2023 19:55, Sam Protsenko wrote:
> On Mon, 6 Mar 2023 at 09:51, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 06/03/2023 15:28, Krzysztof Kozlowski wrote:
>>> On Wed, 22 Feb 2023 22:21:27 -0600, Sam Protsenko wrote:
>>>> As a part of preparation for PM enablement in Exynos850 clock driver,
>>>> this patch series implements CMU_G3D, and also main gate clocks for AUD
>>>> and HSI CMUs. The series brings corresponding changes to bindings, the
>>>> driver and SoC dts file.
>>>>
>>>> Changes in v2:
>>>>   - Rebased all patches on top of the most recent soc/for-next tree
>>>>   - Added A-b and R-b tags
>>>>   - Minor fixes
>>>>
>>>> [...]
>>>
>>> Applied, thanks!
>>>
>>> [1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
>>>       https://git.kernel.org/krzk/linux/c/067ba1605806e52118bb598afb357718df9f0e19
>>> [2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
>>>       https://git.kernel.org/krzk/linux/c/e289665ed0d6df9fca3ebc128f1232d305e4600b
>>> [3/6] clk: samsung: clk-pll: Implement pll0818x PLL type
>>>       https://git.kernel.org/krzk/linux/c/a6feedab8ab9a9e4483deb0bcc87919d92c88b7e
>>> [4/6] clk: samsung: exynos850: Implement CMU_G3D domain
>>>       https://git.kernel.org/krzk/linux/c/c5704a56893b4e77e434597c7c53d878bb3073b0
>>> [5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks
>>>       https://git.kernel.org/krzk/linux/c/d8d12e0d079aff4b1d8079a0a55944c0596f1d67
>>> [6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC
>>>       https://git.kernel.org/krzk/linux/c/ad8f6ad9a4f219950df65731a8ff91baa022c4b0
>>
>> And builds are broken. Please mention in cover letter or commit
>> dependencies and ordering...
>>
> 
> Just checked all most recent commits on your for-next and next/clk
> branches. Seem to build fine for me. AFAIR I checked all patches in
> that series, and I guess there shouldn't be any issues if you apply
> those in the same order they are numbered inside the series. Or you
> mean you have some clash between different series? Anyways, I'm glad
> to help, but I'd need more details on where exactly the problem is (or
> maybe you already fixed it?).

The builds were failing after I applied everything to respective
branches (so DTS separate). I did not notice that your DTS and driver
(both) depend on bindings header constant. This requires special
handling. It actually always required, because it was going through
different trees. Now it goes through my tree, but I still need to handle
it. I reworked the branches and force-pushed, thus you did not see the
exact issue.

Best regards,
Krzysztof
Sam Protsenko March 7, 2023, 5:37 p.m. UTC | #5 
On Tue, 7 Mar 2023 at 01:47, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 06/03/2023 19:55, Sam Protsenko wrote:
> > On Mon, 6 Mar 2023 at 09:51, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 06/03/2023 15:28, Krzysztof Kozlowski wrote:
> >>> On Wed, 22 Feb 2023 22:21:27 -0600, Sam Protsenko wrote:
> >>>> As a part of preparation for PM enablement in Exynos850 clock driver,
> >>>> this patch series implements CMU_G3D, and also main gate clocks for AUD
> >>>> and HSI CMUs. The series brings corresponding changes to bindings, the
> >>>> driver and SoC dts file.
> >>>>
> >>>> Changes in v2:
> >>>>   - Rebased all patches on top of the most recent soc/for-next tree
> >>>>   - Added A-b and R-b tags
> >>>>   - Minor fixes
> >>>>
> >>>> [...]
> >>>
> >>> Applied, thanks!
> >>>
> >>> [1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
> >>>       https://git.kernel.org/krzk/linux/c/067ba1605806e52118bb598afb357718df9f0e19
> >>> [2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
> >>>       https://git.kernel.org/krzk/linux/c/e289665ed0d6df9fca3ebc128f1232d305e4600b
> >>> [3/6] clk: samsung: clk-pll: Implement pll0818x PLL type
> >>>       https://git.kernel.org/krzk/linux/c/a6feedab8ab9a9e4483deb0bcc87919d92c88b7e
> >>> [4/6] clk: samsung: exynos850: Implement CMU_G3D domain
> >>>       https://git.kernel.org/krzk/linux/c/c5704a56893b4e77e434597c7c53d878bb3073b0
> >>> [5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks
> >>>       https://git.kernel.org/krzk/linux/c/d8d12e0d079aff4b1d8079a0a55944c0596f1d67
> >>> [6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC
> >>>       https://git.kernel.org/krzk/linux/c/ad8f6ad9a4f219950df65731a8ff91baa022c4b0
> >>
> >> And builds are broken. Please mention in cover letter or commit
> >> dependencies and ordering...
> >>
> >
> > Just checked all most recent commits on your for-next and next/clk
> > branches. Seem to build fine for me. AFAIR I checked all patches in
> > that series, and I guess there shouldn't be any issues if you apply
> > those in the same order they are numbered inside the series. Or you
> > mean you have some clash between different series? Anyways, I'm glad
> > to help, but I'd need more details on where exactly the problem is (or
> > maybe you already fixed it?).
>
> The builds were failing after I applied everything to respective
> branches (so DTS separate). I did not notice that your DTS and driver
> (both) depend on bindings header constant. This requires special
> handling. It actually always required, because it was going through
> different trees. Now it goes through my tree, but I still need to handle
> it. I reworked the branches and force-pushed, thus you did not see the
> exact issue.
>

Thanks for explaining this. Next time I'll provide the dependencies
info in my patch #0.

> Best regards,
> Krzysztof
>