[v8,0/2] Change mmsys compatible for mt8195 mediatek-drm

Message

Jason-JH.Lin March 6, 2023, 8:06 a.m. UTC

For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.

For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.

Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
and they makes VDOSYS0 supports PQ function while they are not
including in VDOSYS1.

Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component). It makes VDOSYS1 supports the HDR function while it's not
including in VDOSYS0.

To summarize0:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.

Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.
---
Change in v8:
1. Remove mt8192 rdma related modification.

Change in v7:
1. Rebase on v6.2-rc1.
2. Squash patch 1 and 2 in v6.

Change in v6:
1. Add old driver data for mediatek-drm driver with deprecated compatible name.

Change in v5:
1. Add oneOf item to deprecate mediatek,mt8195-mmsys.

Change in v4:
1. Deprecate original mediatek,mt8195-mmsys at the first item.

Change in v3:
1. Keep the original compatible "mediatek,mt8195-mmsys" and add
   "mediatek,mt8195-vdosys0" into the same item to make the tree
   fallback compatible.

Change in v2:
1. Remove Ack tag in the first patch
2. Change the compatible name changing patch to one revert patch and
   one add vdosys0 support patch.
---

Jason-JH.Lin (2):
  drm/mediatek: change mmsys compatible for mt8195 mediatek-drm
  soc: mediatek: remove DDP_DOMPONENT_DITHER from enum

 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 126 +++----------------------
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |   6 --
 include/linux/soc/mediatek/mtk-mmsys.h |   3 +-
 3 files changed, 13 insertions(+), 122 deletions(-)

Comments

AngeloGioacchino Del Regno March 16, 2023, 9:03 a.m. UTC | #1

Il 06/03/23 09:06, Jason-JH.Lin ha scritto:
> For previous MediaTek SoCs, such as MT8173, there are 2 display HW
> pipelines binding to 1 mmsys with the same power domain, the same
> clock driver and the same mediatek-drm driver.
> 
> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
> 2 different power domains, different clock drivers and different
> mediatek-drm drivers.
> 
> Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
> CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
> and they makes VDOSYS0 supports PQ function while they are not
> including in VDOSYS1.
> 
> Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
> component). It makes VDOSYS1 supports the HDR function while it's not
> including in VDOSYS0.
> 
> To summarize0:
> Only VDOSYS0 can support PQ adjustment.
> Only VDOSYS1 can support HDR adjustment.
> 
> Therefore, we need to separate these two different mmsys hardwares to
> 2 different compatibles for MT8195.


Hello Chun-Kuang, Matthias,

Since this series is ready, can you please pick it?

I would imagine that commit [1/2] would go through CK and commit [2/2] goes
through Matthias.

Thanks,
Angelo

Chun-Kuang Hu March 16, 2023, 11:09 a.m. UTC | #2

Hi, Angelo:

AngeloGioacchino Del Regno <[e-mail]> 於
2023年3月16日 週四 下午5:03寫道：
>
> Il 06/03/23 09:06, Jason-JH.Lin ha scritto:
> > For previous MediaTek SoCs, such as MT8173, there are 2 display HW
> > pipelines binding to 1 mmsys with the same power domain, the same
> > clock driver and the same mediatek-drm driver.
> >
> > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
> > 2 different power domains, different clock drivers and different
> > mediatek-drm drivers.
> >
> > Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
> > CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
> > and they makes VDOSYS0 supports PQ function while they are not
> > including in VDOSYS1.
> >
> > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
> > component). It makes VDOSYS1 supports the HDR function while it's not
> > including in VDOSYS0.
> >
> > To summarize0:
> > Only VDOSYS0 can support PQ adjustment.
> > Only VDOSYS1 can support HDR adjustment.
> >
> > Therefore, we need to separate these two different mmsys hardwares to
> > 2 different compatibles for MT8195.
>
>
> Hello Chun-Kuang, Matthias,
>
> Since this series is ready, can you please pick it?
>
> I would imagine that commit [1/2] would go through CK and commit [2/2] goes
> through Matthias.

[1/2] has been applied to mediatek-drm-next [1].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang.

>
> Thanks,
> Angelo
>