mbox series

[v1,00/18] Permission Indirection Extension

Message ID 20230309145246.22787-1-joey.gouly@arm.com (mailing list archive)
Headers show
Series Permission Indirection Extension | expand

Message

Joey Gouly March 9, 2023, 2:52 p.m. UTC 
Hi all,

This series implements the Permission Indirection Extension introduced in 2022
VMSA enhancements [1].

The Permission Indirection Extension is a new way to set memory permissions.
Instead of directly encoding the permission in the Page Table Entry (PTE),
fields in the PTEs are used to index into an array of permissions specified in
a register. This indirection provides greater flexibility, greater encoding
density and enables the representation of new permissions.

The PTEs bit that are repurposed for use with permission indirection are:
	54 PTE_UXN
	53 PTE_PXN
	51 PTE_DBM
	6 PTE_USER

The way that PIE is implemented in this patchset is that the encodings are
picked such that they match how Linux currently sets the bits in the PTEs, so
none of the page table handling has changed. This means this patchset keeps the
same functionality as currently implemented, but allows for future expansion.

Enabling PIE is also a prerequisite for implementing the Guarded Control Stack
Extension (GCS).

Another related extension is the Permission Overlay Extension, which is not
covered by this patch set, but is mentioned in patch 5 as half of PIE encoding
values apply an overlay. However, since overlays are not currently enabled, they
act as all the other permissions do.

This first few patches are adding the new system registers, and cpufeature
capabilities. Then KVM support for save/restore of the new registers is added.
Finally the new Permission Indirection registers are set and the new feature is
enabled.

There's two series on the ML that conflict-ish, but I don't think either will
tough to rework against:
  Kristina's series which changes how HCRX_EL2 works [2]
  Mark's commit to switch HFGxTR to automatic generation [3]

Thanks,
Joey

[1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022
[2] https://lore.kernel.org/linux-arm-kernel/20230216160012.272345-1-kristina.martsenko@arm.com/
[3] https://lore.kernel.org/linux-arm-kernel/20230306-arm64-fgt-reg-gen-v1-1-95bc0c97cfed@kernel.org/

Joey Gouly (18):
  arm64/sysreg: Add ID register ID_AA64MMFR3
  arm64/sysreg: add system registers TCR2_ELx
  arm64/sysreg: add TCR2En to HCRX_EL2
  arm64/sysreg: add HFGxTR_EL2 bits for Permission Indirection Extension
  arm64/sysreg: add PIR*_ELx registers
  arm64: cpufeature: add system register ID_AA64MMFR3
  arm64: cpufeature: add TCR2 cpucap
  arm64: cpufeature: add Permission Indirection Extension cpucap
  KVM: arm64: Save/restore TCR2_EL1
  KVM: arm64: Save/restore PIE registers
  KVM: arm64: expose ID_AA64MMFR3_EL1 to guests
  arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS
  arm64: add PTE_WRITE to PROT_SECT_NORMAL
  arm64: reorganise PAGE_/PROT_ macros
  arm64: disable EL2 traps for PIE
  arm64: add encodings of PIRx_ELx registers
  arm64: enable Permission Indirection Extension (PIE)
  arm64: transfer permission indirection settings to EL2

 arch/arm64/include/asm/cpu.h               |   1 +
 arch/arm64/include/asm/el2_setup.h         |  27 ++++-
 arch/arm64/include/asm/kernel-pgtable.h    |   4 +-
 arch/arm64/include/asm/kvm_host.h          |   5 +
 arch/arm64/include/asm/pgtable-hwdef.h     |   8 ++
 arch/arm64/include/asm/pgtable-prot.h      |  90 ++++++++++-----
 arch/arm64/include/asm/pgtable.h           |   6 +
 arch/arm64/include/asm/sysreg.h            |  23 ++++
 arch/arm64/kernel/cpufeature.c             |  32 ++++++
 arch/arm64/kernel/cpuinfo.c                |   1 +
 arch/arm64/kernel/head.S                   |   8 +-
 arch/arm64/kernel/hyp-stub.S               |  18 +++
 arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h |  12 ++
 arch/arm64/kvm/sys_regs.c                  |   2 +-
 arch/arm64/mm/proc.S                       |  17 ++-
 arch/arm64/tools/cpucaps                   |   2 +
 arch/arm64/tools/sysreg                    | 127 ++++++++++++++++++++-
 17 files changed, 345 insertions(+), 38 deletions(-)

Comments

Mark Brown March 9, 2023, 3:06 p.m. UTC | #1 
On Thu, Mar 09, 2023 at 02:52:29PM +0000, Joey Gouly wrote:

> Add the new ID register ID_AA64MMFR3.

Checking against DDI0601 2022-12.

> +Enum	59:56	ADERR
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum

There is also a 0b0010 which implements FEAT_ADERR.  This probably
suggests that 0b0001 is misnamed - perhaps DEV_ASYNC or something?

> +Enum	55:52	SDERR
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum

Similar comments here.

> +Enum	47:44	ANERR
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	43:40	SNERR
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum

and for these two.
Mark Brown March 17, 2023, 4:49 p.m. UTC | #2 
On Thu, Mar 09, 2023 at 02:52:28PM +0000, Joey Gouly wrote:

> The PTEs bit that are repurposed for use with permission indirection are:
> 	54 PTE_UXN
> 	53 PTE_PXN
> 	51 PTE_DBM
> 	6 PTE_USER

> The way that PIE is implemented in this patchset is that the encodings are
> picked such that they match how Linux currently sets the bits in the PTEs, so
> none of the page table handling has changed. This means this patchset keeps the
> same functionality as currently implemented, but allows for future expansion.

While it's not strictly needed as a result of this patch set since it
aims to implement the same encodings as currently used as soon as we
use any of the new functionality that the extension makes available
we'll need updates to the page table dumping in ptdump.c and task_mmu.c
to decode the indirect encodings natively rather than just relying on
the overlap with the direct encodings.