From patchwork Wed Mar 15 06:23:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13175383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B97FC61DA4 for ; Wed, 15 Mar 2023 06:24:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=2GwNRfrncBirc8NbDLbeLJruIkZk1DUxXu+ZsO5LhuA=; b=v3sd9Dt4l2eRE2 EFNmbMfREBAIRhOwfQJeDlKIcvvQkh4HTMxwt146vyTwYdnLgnnNOwdel/rAtTHH18HqRR6rYPDym jyyfhLs1c9jPF14X7015Z+MieNLAmIegsk/J7d12VWzUyqog5kQzq8m4QcJHdQCI3uTXLsqwR0eqd JiiS23laGWdKeFkl0aGZAAO3da7AINWgb7CNbXN59qKaMWyAO8bQca38xrfRl/A8p5PMtZ53fci5A 6ok3ZpicQaVOmXcc97dfMEHXC9NS3OzEa/Fhsn8RYY9sVipSNRTkwPb/gufXakhqtT5PunqwdWDWV JM6Zvt8eJyajZAwA9shg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pcKXj-00CVVR-2L; Wed, 15 Mar 2023 06:23:23 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pcKXg-00CVUl-07 for linux-arm-kernel@lists.infradead.org; Wed, 15 Mar 2023 06:23:21 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32F6NCrl033939; Wed, 15 Mar 2023 01:23:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1678861392; bh=aEgd9XPuLQCR59sQocm1j89Ty0kcJwLrMZIDQCf67fQ=; h=From:To:CC:Subject:Date; b=gykANu25PYJv0FTC/bkyN5pldAFBEJjn4+n9mO3DTk/loMbdJN5L0B0iOoN9sHp/9 bTManLCL5sCdOg/17uwe4Oiin8l6q1HrH9M7L/4vpVTHZm/J5VNhXZkJxf+YmhMLKN 0/jdFPBCpV64nTmdyrN8Gkuo1u+OGkuTTxBtyj28= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32F6NCnY104448 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 15 Mar 2023 01:23:12 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 15 Mar 2023 01:23:11 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 15 Mar 2023 01:23:11 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32F6N7br024744; Wed, 15 Mar 2023 01:23:08 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v3 0/4] Add DT support for J721E CPSW9G and J7200 CPSW5G Date: Wed, 15 Mar 2023 11:53:03 +0530 Message-ID: <20230315062307.1612220-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230314_232320_179617_D4A05383 X-CRM114-Status: GOOD ( 12.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, This series adds the device-tree nodes for the CPSW9G instance of CPSW Ethernet Switch on TI's J721E SoC and the CPSW5G instance of CPSW Ethernet Switch on TI's J7200 SoC. Additionally, overlays are also added to individually enable CPSW9G on J721E SoC and CPSW5G on J7200 SoC in QSGMII mode with the Add-On J7 QUAD Port Ethernet expansion QSGMII daughtercard. This series combines the v2 series for J721E CPSW9G at: https://lore.kernel.org/r/20230310103504.731845-1-s-vadapalli@ti.com/ and the v1 series for J7200 CPSW5G at: https://lore.kernel.org/r/20230310101407.722334-1-s-vadapalli@ti.com/ The suggestions for the v2 series for J721E are implemented for the J7200 series as well in this patch series. Reviewed-by: Andrew Davis --- Changes from v2 for J721E CPSW9G series: 1. Rename the overlay k3-j721e-quad-port-eth-exp.dtso as k3-j721e-evm-quad-port-eth-exp.dtso. 2. Update arch/arm64/boot/dts/ti/Makefile to build k3-j721e-evm.dtb as the result of applying k3-j721e-evm-quad-port-eth-exp.dtbo to k3-j721e-common-proc-board.dtb. 3. Use the newer "&{/} {" style instead of the "fragments" style in k3-j721e-evm-quad-port-eth-exp.dtso. 4. Move the "mdio0_pins_default" pinctrl from cpsw0 node into the "cpsw9g_mdio" node. 5. Disable individual "cpsw0_port" nodes in the main.dtsi file, enabling only the required nodes in the overlay. 6. Disable the "cpsw9g_mdio" node in the main.dtsi file. Changes from v1 for J721E CPSW9G series: 1. Rename node name "mdio_pins_default" to "mdio0-pins-default", since node names shouldn't contain underscores. 2. Change node label "mdio_pins_default" to "mdio0_pins_default". Changes from v1 for J7200 CPSW5G series: 1. Rename the overlay k3-j7200-quad-port-eth-exp.dtso as k3-j7200-evm-quad-port-eth-exp.dtso. 2. Update arch/arm64/boot/dts/ti/Makefile to build k3-j7200-evm.dtb as the result of applying k3-j7200-evm-quad-port-eth-exp.dtbo to k3-j7200-common-proc-board.dtb. 3. Use the newer "&{/} {" style instead of the "fragments" style in k3-j7200-evm-quad-port-eth-exp.dtso. 4. Move the "mdio0_pins_default" pinctrl from cpsw0 node into the "cpsw5g_mdio" node. 5. Disable individual "cpsw0_port" nodes in the main.dtsi file, enabling only the required nodes in the overlay. 6. Disable the "cpsw5g_mdio" node in the main.dtsi file. J721E CPSW9G v2 series: https://lore.kernel.org/r/20230310103504.731845-1-s-vadapalli@ti.com/ J721E CPSW9G v1 series: https://lore.kernel.org/r/20230310092804.692303-1-s-vadapalli@ti.com/ J7200 CPSW5G v1 series: https://lore.kernel.org/r/20230310101407.722334-1-s-vadapalli@ti.com/ Siddharth Vadapalli (4): arm64: dts: ti: k3-j721e: Add CPSW9G nodes arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode arm64: dts: ti: j7200-main: Add CPSW5G nodes arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII mode arch/arm64/boot/dts/ti/Makefile | 6 +- .../ti/k3-j7200-evm-quad-port-eth-exp.dtso | 100 +++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 88 ++++++++++++ .../ti/k3-j721e-evm-quad-port-eth-exp.dtso | 132 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 116 +++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 + 6 files changed, 441 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso