mbox series

[v2,00/19] Permission Indirection Extension

Message ID 20230413110513.243326-1-joey.gouly@arm.com (mailing list archive)
Headers show
Series Permission Indirection Extension | expand

Message

Joey Gouly April 13, 2023, 11:04 a.m. UTC 
Hi all,

This series implements the Permission Indirection Extension introduced in 2022
VMSA enhancements [1].

Changes since v1 [2]:
	- Renamed PIRx_ELx_PERMIDX and reversed the arguments
	- Added new registers to get-reg-list selftest
	- Added booting requirements
	- Add TCR2_EL2 and PIR_EL2 registers
	- Collected review tags
	- Rebased onto arm64/for-next/core (b2ad9d4e249), to get Mark Brown's
	  HFG* register commit.

The Permission Indirection Extension is a new way to set memory permissions.
Instead of directly encoding the permission in the Page Table Entry (PTE),
fields in the PTEs are used to index into an array of permissions specified in
a register. This indirection provides greater flexibility, greater encoding
density and enables the representation of new permissions.

The PTEs bit that are repurposed for use with permission indirection are:
	54 PTE_UXN
	53 PTE_PXN
	51 PTE_DBM
	6 PTE_USER

The way that PIE is implemented in this patchset is that the encodings are
picked such that they match how Linux currently sets the bits in the PTEs, so
none of the page table handling has changed. This means this patchset keeps the
same functionality as currently implemented, but allows for future expansion.

Enabling PIE is also a prerequisite for implementing the Guarded Control Stack
Extension (GCS).

Another related extension is the Permission Overlay Extension, which is not
covered by this patch set, but is mentioned in patch 5 as half of PIE encoding
values apply an overlay. However, since overlays are not currently enabled, they
act as all the other permissions do.

This first few patches are adding the new system registers, and cpufeature
capabilities. Then KVM support for save/restore of the new registers is added.
Finally the new Permission Indirection registers are set and the new feature is
enabled.

Kristina's series [3] changes how HCRX_EL2 is handled, so there will be need to be
some minor changes, depending on which series goes in first.

Thanks,
Joey

Joey Gouly (19):
  arm64/sysreg: Add ID register ID_AA64MMFR3
  arm64/sysreg: add system registers TCR2_ELx
  arm64/sysreg: update HCRX_EL2 register
  arm64/sysreg: add PIR*_ELx registers
  arm64: cpufeature: add system register ID_AA64MMFR3
  arm64: cpufeature: add TCR2 cpucap
  arm64: cpufeature: add Permission Indirection Extension cpucap
  KVM: arm64: Save/restore TCR2_EL1
  KVM: arm64: Save/restore PIE registers
  KVM: arm64: expose ID_AA64MMFR3_EL1 to guests
  arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS
  arm64: add PTE_WRITE to PROT_SECT_NORMAL
  arm64: reorganise PAGE_/PROT_ macros
  arm64: disable EL2 traps for PIE
  arm64: add encodings of PIRx_ELx registers
  arm64: enable Permission Indirection Extension (PIE)
  arm64: transfer permission indirection settings to EL2
  arm64: Document boot requirements for PIE
  KVM: selftests: get-reg-list: add Permission Indirection registers

 Documentation/arm64/booting.rst               |  26 +++
 arch/arm64/include/asm/cpu.h                  |   1 +
 arch/arm64/include/asm/el2_setup.h            |  23 ++-
 arch/arm64/include/asm/kernel-pgtable.h       |   4 +-
 arch/arm64/include/asm/kvm_host.h             |   5 +
 arch/arm64/include/asm/pgtable-hwdef.h        |   8 +
 arch/arm64/include/asm/pgtable-prot.h         |  96 ++++++++---
 arch/arm64/include/asm/sysreg.h               |  19 +++
 arch/arm64/kernel/cpufeature.c                |  32 ++++
 arch/arm64/kernel/cpuinfo.c                   |   1 +
 arch/arm64/kernel/head.S                      |   8 +-
 arch/arm64/kernel/hyp-stub.S                  |  18 ++
 arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h    |  12 ++
 arch/arm64/kvm/sys_regs.c                     |   5 +-
 arch/arm64/mm/proc.S                          |  17 +-
 arch/arm64/tools/cpucaps                      |   2 +
 arch/arm64/tools/sysreg                       | 159 +++++++++++++++++-
 .../selftests/kvm/aarch64/get-reg-list.c      |   5 +-
 18 files changed, 402 insertions(+), 39 deletions(-)

Comments

Mark Brown April 13, 2023, 11:14 a.m. UTC | #1 
On Thu, Apr 13, 2023 at 12:04:55PM +0100, Joey Gouly wrote:
> Add the new ID register ID_AA64MMFR3.

DDI0601 2023-03 has a few more values which this misses, it looks like
this might have been done against DDO0601 2022-12?  Ideally we'd update
to the new version but it's not urgent so:

Reviewed-by: Mark Brown <broonie@kernel.org>

It's good to note what version of the architecture you're syncing with.

> +Enum	59:56	ADERR
> +	0b0000	NI
> +	0b0001	DEV_ASYNC
> +	0b0010	FEAT_ADERR
> +EndEnum

There's also 0b0011 which on a quick scan I'm not sure what a clear name
for is.

> +Enum	55:52	SDERR
> +	0b0000	NI
> +	0b0001	DEV_SYNC
> +	0b0001	FEAT_SDERR
> +EndEnum

Similar pattern to ADERR here.

> +Res0	51:48
> +Enum	47:44	ANERR
> +	0b0000	ASYNC
> +	0b0001	FEAT_ANERR
> +EndEnum

There's also 0b0010 and 0b0011 for this.

> +Enum	43:40	SNERR
> +	0b0000	SYNC
> +	0b0001	FEAT_SNERR
> +EndEnum

Similar pattern to ANERR here.
Joey Gouly April 13, 2023, 11:25 a.m. UTC | #2 
On Thu, Apr 13, 2023 at 12:14:59PM +0100, Mark Brown wrote:
> On Thu, Apr 13, 2023 at 12:04:55PM +0100, Joey Gouly wrote:
> > Add the new ID register ID_AA64MMFR3.
> 
> DDI0601 2023-03 has a few more values which this misses, it looks like
> this might have been done against DDO0601 2022-12?  Ideally we'd update
> to the new version but it's not urgent so:
> 
> Reviewed-by: Mark Brown <broonie@kernel.org>
> 
> It's good to note what version of the architecture you're syncing with.
> 
> > +Enum	59:56	ADERR
> > +	0b0000	NI
> > +	0b0001	DEV_ASYNC
> > +	0b0010	FEAT_ADERR
> > +EndEnum
> 
> There's also 0b0011 which on a quick scan I'm not sure what a clear name
> for is.
> 
> > +Enum	55:52	SDERR
> > +	0b0000	NI
> > +	0b0001	DEV_SYNC
> > +	0b0001	FEAT_SDERR
> > +EndEnum
> 
> Similar pattern to ADERR here.
> 
> > +Res0	51:48
> > +Enum	47:44	ANERR
> > +	0b0000	ASYNC
> > +	0b0001	FEAT_ANERR
> > +EndEnum
> 
> There's also 0b0010 and 0b0011 for this.
> 
> > +Enum	43:40	SNERR
> > +	0b0000	SYNC
> > +	0b0001	FEAT_SNERR
> > +EndEnum
> 
> Similar pattern to ANERR here.

Yes I was doing this against a 2022-12 version.

I completely messed up this section though, looks like I accidentaly got rid of
all the `0b0000 NI` values. Will redo this part.

Thanks,
Joey