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[RFC,0/1] arm64: dts: ti: k3-j721s2: handling subnode of msmc node

Message ID 20230503144706.1265672-1-u-kumar1@ti.com (mailing list archive)
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Series arm64: dts: ti: k3-j721s2: handling subnode of msmc node | expand

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Kumar, Udit May 3, 2023, 2:47 p.m. UTC 
TI K3 SOCs have msmc sram, part of it can be configured as L3 cache
depending upon system firmware configuration file.

This could be possible to have no L3 cache or variable size of
L3 cache.
In either case top of 64KB of SRAM has to be reserved for system
firmware called tifs.

https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html?highlight=msmc
Section: TISCI_MSG_QUERY_MSMC.

But u-boot as part of fix up is deleting sysfw and l3cache node
before passing DT to OS
https://github.com/u-boot/u-boot/blob/master/arch/arm/mach-k3/common.c#L412

In my view we can handle in two ways
1) delete tifs node as well
In this case, only accessible sram will be visible to OS
https://lore.kernel.org/all/20230420081128.3617214-1-u-kumar1@ti.com/

2) make these nodes (tifs, atf and l3cache) as reserved,
so that OS has complete view of memory.
This is patch for option 2.

Nishanth suggested to discuss in k.org group
https://lore.kernel.org/all/20230502230022.5pjywy6h7oqrkmwh@elusive/

So sending this patch for suggestion for selection right option.
Also other options are welcome.


Udit Kumar (1):
  arm64: dts: ti: k3-j721s2: Add reserved status in msmc node.

 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 3 +++
 1 file changed, 3 insertions(+)