From patchwork Fri Aug 11 03:45:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13350049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63EF5C001E0 for ; Fri, 11 Aug 2023 03:46:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ShrBs2la7/zEocdS3uUu+d75finkElG6qm8XY0LaPg4=; b=usHyddMvM11g5X B0dEMDvzXbLnbUa0ETniQ5F7ZEav7tj/CSiDM53KX7UhwxNuHN1rmqUIy7XwnCWK90HoL6frX+Gzs SxnlROxkyhIlCMZTrmZLAM4KJPuM8AR3MLFqWIH5yDx8N3LYreJNB4vTyz8elATMzHohwY2XrGd5P /AB9ooBaezeW1wg4H8+MeVxMuGe2ZqYZF+GfTsSCZIyjryLhImhf0szmqTQAasa1zJwMAx5Wdal6I oE+fhyBebsobGeA0uvf4zbiN14ErB9H1yIU4CSmBofmsCkrNPqxcJeUlNqBxXTKnBHg0QnaTco1WX 6VvX2ioG/dwwRcXWENkg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qUJ6O-009J3Y-2B; Fri, 11 Aug 2023 03:46:16 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qUJ6L-009J2S-08 for linux-arm-kernel@lists.infradead.org; Fri, 11 Aug 2023 03:46:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1B550D75; Thu, 10 Aug 2023 20:46:53 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.54.13]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4F1E33F6C4; Thu, 10 Aug 2023 20:46:06 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 0/3] coresight: etm: Make cycle count threshold user configurable Date: Fri, 11 Aug 2023 09:15:57 +0530 Message-Id: <20230811034600.944386-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230810_204613_143397_4C9EB209 X-CRM114-Status: UNSURE ( 8.60 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series makes ETM TRCCCCTRL based 'cc_threshold' user configurable via the perf event attribute. But first, this implements an errata work around affecting ETM TRCIDR3.CCITMIN value on certain cpus, overriding the field. This series applies on v6.5-rc5. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Leo Yan Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Changes in V3: - Added errata work around affecting TRCIDR3.CCITMIN - Split the document update into a separate patch Changes in V2: https://lore.kernel.org/all/20230808074533.380537-1-anshuman.khandual@arm.com/ - s/treshhold/threshold Changes in V1: https://lore.kernel.org/all/20230804044720.1478900-1-anshuman.khandual@arm.com/ Anshuman Khandual (3): coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus coresight: etm: Make cycle count threshold user configurable Documentation: coresight: Add cc_threshold tunable Documentation/arch/arm64/silicon-errata.rst | 10 ++++ Documentation/trace/coresight/coresight.rst | 4 ++ .../hwtracing/coresight/coresight-etm-perf.c | 2 + .../coresight/coresight-etm4x-core.c | 49 ++++++++++++++++++- 4 files changed, 63 insertions(+), 2 deletions(-)