From patchwork Wed Sep 6 09:41:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 13375517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51CBAEB8FA5 for ; Wed, 6 Sep 2023 10:46:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3g4u0P1BeXlX57RcXioMjVmIA/9K9IZpmMWbE7+w8rA=; b=LNVuqR/POe522Z aKE5XLGS4je0tIE3DZPutQsTNxu+eUjH2ESDoyss06B1PARF2rbLcZ+F/OkSUKx64bv7/mFgVVCt8 kly5fhn1E5oC0fIrpeY7b2cdwbiAD+BzEuU5vuB5V0DCbXfQunLZu9462Y36JPKNx6W0a42fv/pjZ 5uXcVNeCUlRRCy6QOabSsr3KfybWmTYtJ2WlsW7bUlZGUpmUfx8yhgVDa9L/UV+8COetjxB2BtLsm C+OVxDNfKPnVNEW9fQd9yptv1foWarIEG91F/aZCX6f57qbKSSsq7A1Ix//JS2bfi2yjzfW2IQtEO bdYZ1NVbulC7dmLcNZaw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qdq2h-008Hav-2j; Wed, 06 Sep 2023 10:45:51 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qdp2n-007y5F-2m for linux-arm-kernel@lists.infradead.org; Wed, 06 Sep 2023 09:41:55 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id B6289CE13C8; Wed, 6 Sep 2023 09:41:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B14B7C433C7; Wed, 6 Sep 2023 09:41:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1693993307; bh=oCKfqMVNrxKpZHzFqM4z491hl+uPYruxSgEUicAfYlI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IPfvt3V8gQEtfMQf2/0frKr6SedXyogmBexVdS1IpDWWUMYEtBEknaayZlXgNoWvd Q8BlxFe5JQJoT8K17x7MbfkCq2wFRMBErHwCI49t+jGx/+uptK69GngE/FFtpphSXD GCKMX9xRyvlGNfVP+0m7rxCjmtpP6aacMbVjbAJFB/F325KxDeCSDKfF7BQYkICXWG Omo2C+vDpTHmf0+BB0POnecJZQs9JgO/P15bXywSN0VuCrblZrEvy+ZMK8WR9APREi UfV2uOdH2NITAKYSIGnvLCJvOPP+mFfjf2nCx9Kf5bqLKj1YdimM/W/jZAGPQEXk5t Qgm8oCuAyvOgA== From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Mark Rutland , Robin Murphy , Rob Herring , Fang Xiang , Marc Zyngier Subject: [PATCH v2 0/2] irqchip/gic-v3: Enable non-coherent GIC designs probing Date: Wed, 6 Sep 2023 11:41:37 +0200 Message-Id: <20230906094139.16032-1-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905104721.52199-1-lpieralisi@kernel.org> References: <20230905104721.52199-1-lpieralisi@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230906_024154_125937_E04C8DD3 X-CRM114-Status: GOOD ( 13.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series is v2 of a previous version[1]. v1 -> v2: - Updated DT bindings as per feedback - Updated patch[2] to use GIC quirks infrastructure [1] https://lore.kernel.org/all/20230905104721.52199-1-lpieralisi@kernel.org Original cover letter --- The GICv3 architecture specifications provide a means for the system programmer to set the shareability and cacheability attributes the GIC components (redistributors and ITSes) use to drive memory transactions. Albeit the architecture give control over shareability/cacheability memory transactions attributes (and barriers), it is allowed to connect the GIC interconnect ports to non-coherent memory ports on the interconnect, basically tying off shareability/cacheability "wires" and de-facto making the redistributors and ITSes non-coherent memory observers. This series aims at starting a discussion over a possible solution to this problem, by adding to the GIC device tree bindings the standard dma-noncoherent property. The GIC driver uses the property to force the redistributors and ITSes shareability attributes to non-shareable, which consequently forces the driver to use CMOs on GIC memory tables. On ARM DT DMA is default non-coherent, so the GIC driver can't rely on the generic DT dma-coherent/non-coherent property management layer (of_dma_is_coherent()) which would default all GIC designs in the field as non-coherent; it has to rely on ad-hoc dma-noncoherent property handling. When a consistent approach is agreed upon for DT an equivalent binding will be put forward for ACPI based systems. Lorenzo Pieralisi (2): dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property irqchip/gic-v3: Enable non-coherent redistributors/ITSes probing .../interrupt-controller/arm,gic-v3.yaml | 12 +++++++++++ drivers/irqchip/irq-gic-common.h | 4 ++++ drivers/irqchip/irq-gic-v3-its.c | 21 +++++++++++++++---- drivers/irqchip/irq-gic-v3.c | 13 ++++++++++++ 4 files changed, 46 insertions(+), 4 deletions(-)