From patchwork Thu Sep 7 02:16:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13376085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 871C7EE14A9 for ; Thu, 7 Sep 2023 02:19:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=m7w5zyEsoadIQubPt7O6GNT/o14sUBads5izgD+i5fo=; b=Eck08KZ3YXAGsF v4KUmezGwfh6m9+SADBcLXGAez8R/M4qom7Y7xe5IIq4rBZBd3YdEfDbyv7SvOCy0Bau4g4ZMwFKd /4rNq/7bth9NavGbzEIc8ze+sD+v2X7a3ND/i7FzpgDk8HMCCBwLZ6tjKJojhdNUfHEBpHzy+vLn7 tb97yH+bCrYRqZAqjFG8TyYEbnKXWE4Srz4LsEjS+k27F7OUl//wwud5lwIuowk6+thr0OTAM0knC ta+hcOXRdX8Ul2zJYvH8DLC3RvwvxsDHWWmXyJjxi5OqWnY3P7F18aVtioUaIgX0pF7vnb9rLKWVI pGFAtP5Hhxmb3iIK4IRQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qe4bX-00BBJ6-2o; Thu, 07 Sep 2023 02:18:47 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qe4bS-00BBHM-2x; Thu, 07 Sep 2023 02:18:45 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3872I5eM024097; Thu, 7 Sep 2023 10:18:05 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 7 Sep 2023 10:18:00 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , CC: , , , , , , , , , , Yu Chien Peter Lin Subject: [PATCH 0/4] Support Andes PMU extension Date: Thu, 7 Sep 2023 10:16:31 +0800 Message-ID: <20230907021635.1002738-1-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3872I5eM024097 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230906_191843_393281_4E331A95 X-CRM114-Status: GOOD ( 10.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch series introduces the Andes PMU errata, which adds support for perf sampling and mode filtering with the Andes PMU extension. The custom PMU extension serves the same purpose as Sscofpmf. Its non-standard local interrupt is assigned to bit 18 in the custom S-mode local interrupt pending CSR (slip), while the interrupt cause is (256 + 18). This series is dependent on the series from Prabhakar, - https://patchwork.kernel.org/project/linux-riscv/cover/20230818135723.80612-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ The feature needs the PMU device callbacks in OpenSBI. The OpenSBI and Linux patches can be found on Andes Technology GitHub - https://github.com/andestech/opensbi/commits/andes-pmu-support - https://github.com/andestech/linux/commits/andes-pmu-support The PMU device tree node of AX45MP: - https://github.com/andestech/opensbi/blob/andes-pmu-support/docs/pmu_support.md#example-3 Tested hardware: - ASUS Tinker-V (RZ/Five, AX45MP single core) - Andes AE350 (AX45MP quad core) Locus Wei-Han Chen (1): riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin (3): riscv: errata: Rename defines for Andes irqchip/riscv-intc: Support large non-standard hwirq number riscv: errata: Add Andes PMU errata arch/riscv/Kconfig.errata | 13 ++ arch/riscv/errata/andes/errata.c | 55 +++++++- arch/riscv/include/asm/errata_list.h | 45 ++++++- arch/riscv/include/asm/vendorid_list.h | 2 +- arch/riscv/kernel/alternative.c | 2 +- drivers/irqchip/irq-riscv-intc.c | 10 +- drivers/perf/riscv_pmu_sbi.c | 20 ++- .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++ .../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++ .../arch/riscv/andes/ax45/memory.json | 57 ++++++++ .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++ tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + 12 files changed, 453 insertions(+), 24 deletions(-) create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json