| Message ID | 20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add new Renesas RZ/G3S SoC and RZ/G3S SMARC EVK | expand |
On Tue, Sep 12, 2023 at 6:52 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: > This patch series adds initial support for The Renesas RZ/G3S (R9A08G045{S33}) > SoC. The RZ/G3S device is a general-purpose microprocessor with a > single-core Arm® Cortex®-A55 (1.1GHz) and a dual-core Arm® Cortex®-M33 (250MHz), > perfect for an IOT gateway controller. I saw some of the patches are fixes. I expect that you and Geert figure these out so I can get a separate pull request for those ASAP. (Unless they are nonurgent.) For new code try to use <linux/cleanup.h>. Or if you prefer take a sweep and introduce scoped guards everywhere (for spinlocks, mutexes..). Yours, Linus Walleij
Hi Linus, On Tue, Sep 12, 2023 at 10:55 AM Linus Walleij <linus.walleij@linaro.org> wrote: > For new code try to use <linux/cleanup.h>. > Or if you prefer take a sweep and introduce scoped guards > everywhere (for spinlocks, mutexes..). Hmmm, <linux/cleanup.h> is only available in v6.5 and later. I don't know whether the CiP machinery is planning to backport <linux/cleanup.h> to e.g. v6.1 LTS... Gr{oetje,eeting}s, Geert
On Tue, Sep 12, 2023 at 11:03 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Tue, Sep 12, 2023 at 10:55 AM Linus Walleij <linus.walleij@linaro.org> wrote: > > For new code try to use <linux/cleanup.h>. > > Or if you prefer take a sweep and introduce scoped guards > > everywhere (for spinlocks, mutexes..). > > Hmmm, <linux/cleanup.h> is only available in v6.5 and later. > I don't know whether the CiP machinery is planning to backport > <linux/cleanup.h> to e.g. v6.1 LTS... Only for new code! (for-v6.7+) Yours, Linus Walleij
Hi, Linus, On 12.09.2023 12:05, Linus Walleij wrote: > On Tue, Sep 12, 2023 at 11:03 AM Geert Uytterhoeven > <geert@linux-m68k.org> wrote: >> On Tue, Sep 12, 2023 at 10:55 AM Linus Walleij <linus.walleij@linaro.org> wrote: > >>> For new code try to use <linux/cleanup.h>. >>> Or if you prefer take a sweep and introduce scoped guards >>> everywhere (for spinlocks, mutexes..). >> >> Hmmm, <linux/cleanup.h> is only available in v6.5 and later. >> I don't know whether the CiP machinery is planning to backport >> <linux/cleanup.h> to e.g. v6.1 LTS... > > Only for new code! (for-v6.7+) Would you prefer <linux/cleanup.h> even if the new code just uses the already existing spinlocks, mutexes? Or only for new code that introduces new spinlocks, mutexes? Thank you, Claudiu Beznea > > Yours, > Linus Walleij
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Hi, This patch series adds initial support for The Renesas RZ/G3S (R9A08G045{S33}) SoC. The RZ/G3S device is a general-purpose microprocessor with a single-core Arm® Cortex®-A55 (1.1GHz) and a dual-core Arm® Cortex®-M33 (250MHz), perfect for an IOT gateway controller. This includes: - SoC identification; - clocks (core clocks, pin controller clock, serial interface, SD ch0 clock) and corresponding resets; - minimal device tree for SoM and carrier boards. With this series Linux can boot from eMMC or SD card. The eMMC and uSD interface are multiplexed on the SoM; selection is made using a hardware switch. Patches are gouped as follows: - 01-04 adds SoC identification support; - 05 is a simple cleanup on SoC identification support - 06-09 contain fixes on clock drivers identified while adding RZ/G3S support - 10-14 clock cleanups identifies while adding support for RZ/G3S - 15-22 clock changes needed by RZ/G3S - 23-30 pinctrl changes needed by RZ/G3S - 31 document SDHI for RZ/G3S - 32-37 device tree support for RZ/G3S Thank you, Claudiu Beznea Claudiu Beznea (37): dt-bindings: serial: renesas,scif: document r9a08g045 support dt-bindings: soc: renesas: document Renesas RZ/G3S SoC variants dt-bindings: soc: renesas: renesas,rzg2l-sysc: document RZ/G3S SoC soc: renesas: identify RZ/G3S SoC soc: renesas: remove blank lines clk: renesas: rzg2l: wait for status bit of SD mux before continuing clk: renesas: rzg2l: lock around writes to mux register clk: renesas: rzg2l: trust value returned by hardware clk: renesas: rzg2l: fix computation formula clk: renesas: rzg2l: use core->name for clock name clk: renesas: rzg2l: simplify a bit the logic in rzg2l_mod_clock_endisable() clk: renesas: rzg2l: reduce the critical area clk: renesas: rzg2l: use FIELD_GET() for PLL register fields clk: renesas: rzg2l: use u32 for flag and mux_flags clk: renesas: rzg2l: add support for RZ/G3S PLL clk: renesas: rzg2l: add struct clk_hw_data clk: renesas: rzg2l: remove CPG_SDHI_DSEL from generic header clk: renesas: rzg2l: refactor sd mux driver clk: renesas: rzg2l: add a divider clock for RZ/G3S dt-bindings: clock: renesas,rzg2l-cpg: document RZ/G3S SoC dt-bindings: clock: add r9a08g045 CPG clocks and resets definitions clk: renesas: add minimal boot support for RZ/G3S SoC pinctrl: renesas: rzg2l: index all registers based on port offset pinctrl: renesas: rzg2l: adapt for different SD/PWPR register offsets pinctrl: renesas: rzg2l: adapt function number for RZ/G3S pinctrl: renesas: rzg2l: move ds and oi to SoC specific configuration pinctrl: renesas: rzg2l: add support for different ds values on different groups pinctrl: renesas: rzg2l: make struct rzg2l_pinctrl_data::dedicated_pins constant dt-bindings: pinctrl: renesas: document RZ/G3S SoC pinctrl: renesas: rzg2l: add support for RZ/G3S SoC dt-bindings: mmc: renesas,sdhi: Document RZ/G3S support arm64: dts: renesas: add initial DTSI for RZ/G3S SoC arm64: dts: renesas: rzg3l-smarc-som: add initial support for RZ/G3S SMARC Carrier-II SoM arm64: dts: renesas: rzg3s-smarc: add initial device tree for RZ SMARC Carrier-II Board dt-bindings: arm: renesas: document SMARC Carrier-II EVK arm64: dts: renesas: r9a08g045s33-smarc: add initial device tree for RZ/G3S SMARC EVK board arm64: defconfig: enable RZ/G3S (R9A08G045) SoC .../bindings/clock/renesas,rzg2l-cpg.yaml | 1 + .../devicetree/bindings/mmc/renesas,sdhi.yaml | 2 + .../pinctrl/renesas,rzg2l-pinctrl.yaml | 26 +- .../bindings/serial/renesas,scif.yaml | 1 + .../soc/renesas/renesas,rzg2l-sysc.yaml | 1 + .../bindings/soc/renesas/renesas.yaml | 8 + arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 139 ++++ .../boot/dts/renesas/r9a08g045s33-smarc.dts | 17 + arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi | 14 + .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 147 ++++ arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 28 + arch/arm64/configs/defconfig | 1 + drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a07g043-cpg.c | 19 +- drivers/clk/renesas/r9a07g044-cpg.c | 19 +- drivers/clk/renesas/r9a08g045-cpg.c | 217 ++++++ drivers/clk/renesas/rzg2l-cpg.c | 495 ++++++++++-- drivers/clk/renesas/rzg2l-cpg.h | 39 +- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 728 ++++++++++++++---- drivers/soc/renesas/Kconfig | 6 + drivers/soc/renesas/renesas-soc.c | 15 +- include/dt-bindings/clock/r9a08g045-cpg.h | 243 ++++++ 24 files changed, 1924 insertions(+), 252 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi create mode 100644 drivers/clk/renesas/r9a08g045-cpg.c create mode 100644 include/dt-bindings/clock/r9a08g045-cpg.h