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[v7,0/4] perf: arm_cspmu: ampere: Add support for Ampere SoC PMUs

Message ID 20230913233941.9814-1-ilkka@os.amperecomputing.com (mailing list archive)
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Series perf: arm_cspmu: ampere: Add support for Ampere SoC PMUs | expand

Message

Ilkka Koskinen Sept. 13, 2023, 11:39 p.m. UTC 
Changes since v6:
    * Rebased on top of Besar's updated patch

      [PATCH v6] perf: arm_cspmu: Separate Arm and vendor module
      https://lore.kernel.org/all/20230821231608.50911-1-bwicaksono@nvidia.com/

    * Changed Ampere specific module to use ida/ida_alloc() instead of idr/idr_alloc()

Changes since v5:
    * Implemented the needed parts for vendor registration API
        * Rebased on top of Besar's patch

      [PATCH v5] perf: arm_cspmu: Separate Arm and vendor module
            https://lore.kernel.org/all/20230705104745.52255-1-bwicaksono@nvidia.com/

    * v5: https://lore.kernel.org/all/20230714010141.824226-1-ilkka@os.amperecomputing.com/

Changes since v4:
    * "Support implementation specific filters" patch:
            - Added comment about filter and impdef registers and reference
	              to the Coresight PMU specification to the commit message

    * "Add support for Ampere SoC PMU" patch:
      - Fixed the documentation and added more comments
              - Changed the incrementing PMU index number to idr_alloc()
	      	  (Needs a impdef release hook patch to release unused index)
		  	 - Fixed style in init_ops() to more reasonable
			   - Moved bank parameter to config1

Changes since v3:
    * use_64b_counter_reg => has_atomic_dword (patch 1/4)
        * Removed the unnecessary hook for group validation (patch 3/4)
	    * Added group config validation to ampere_cspmu_validate_event() (patch 4/4)
	        * Rebased the patchset

Changes since v2:
    * Changed to use supports_64bits_atomics() and replaced the split writes
          with lo_hi_writeq()
	      * Added implementation specific group validation to patch 3
	          * Dropped shared interrupt patch
		      * Removed unnecessary filter_enable parameter from ampere module
		          * Added group validation to ampere module

Changes since v1:
    * Rather than creating a completely new driver, implemented as a submodule
          of Arm CoreSight PMU driver
	        * Fixed shared filter handling

Ilkka Koskinen (4):
  perf: arm_cspmu: Split 64-bit write to 32-bit writes
  perf: arm_cspmu: Support implementation specific filters
  perf: arm_cspmu: Support implementation specific validation
  perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU

 .../admin-guide/perf/ampere_cspmu.rst         |  29 ++
 drivers/perf/arm_cspmu/Kconfig                |  10 +
 drivers/perf/arm_cspmu/Makefile               |   2 +
 drivers/perf/arm_cspmu/ampere_cspmu.c         | 271 ++++++++++++++++++
 drivers/perf/arm_cspmu/arm_cspmu.c            |  33 ++-
 drivers/perf/arm_cspmu/arm_cspmu.h            |   7 +
 6 files changed, 346 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/admin-guide/perf/ampere_cspmu.rst
 create mode 100644 drivers/perf/arm_cspmu/ampere_cspmu.c

Comments

Will Deacon Oct. 9, 2023, 4:56 p.m. UTC | #1 
On Wed, 13 Sep 2023 16:39:37 -0700, Ilkka Koskinen wrote:
> Changes since v6:
>     * Rebased on top of Besar's updated patch
> 
>       [PATCH v6] perf: arm_cspmu: Separate Arm and vendor module
>       https://lore.kernel.org/all/20230821231608.50911-1-bwicaksono@nvidia.com/
> 
>     * Changed Ampere specific module to use ida/ida_alloc() instead of idr/idr_alloc()
> 
> [...]

Applied to will (for-next/perf), thanks!

[1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes
      https://git.kernel.org/will/c/8c282414ca62
[2/4] perf: arm_cspmu: Support implementation specific filters
      https://git.kernel.org/will/c/0a7603ab242e
[3/4] perf: arm_cspmu: Support implementation specific validation
      https://git.kernel.org/will/c/647d5c5a9e76
[4/4] perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU
      https://git.kernel.org/will/c/290a9c0e55f8

Cheers,