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[v4,0/2] arm64: dts: ti: k3-j7200: Fixes for various dtbs_checks warnings

Message ID 20231009082452.30684-1-vaishnav.a@ti.com (mailing list archive)
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Series arm64: dts: ti: k3-j7200: Fixes for various dtbs_checks warnings | expand

Message

Vaishnav Achath Oct. 9, 2023, 8:24 a.m. UTC 
Hi,

Few fixups for j7200 dtbs_check warnings.

This is V4 for the following series rebased and tested with 6.6-rc5,

V3 : https://lore.kernel.org/all/20230513101343.785-1-vaishnav.a@ti.com
V2 : https://lore.kernel.org/all/20230505115858.7391-1-vaishnav.a@ti.com/
V1 : https://lore.kernel.org/all/20230424173623.477577-1-nm@ti.com/

Bootlog with basic hyperflash testing (6.6.0-rc5-next-20231009):
https://gist.github.com/vaishnavachath/f7265e932725fd992dbc4e48b993e9c0

Patch 2/2 depends on the following patch under review which enables reg-mux
to be used when parent node is not syscon :
https://lore.kernel.org/all/20230911151030.71100-1-afd@ti.com/

Changelog:

V3->V4:
  * Rebase and tested with 6.6-rc5

V2->V3:
  * Drop pinctrl fix patch as the fix [2]  is already merged to next.
  * Keep register regions unchanged as it is correct according to memory
  map, update commit message.

V1->V2:
 * Address feedback as recommended in [3].
 * Address feedback from Udit to limit the FSS register region size as
 per TRM.
 * Use reg-mux changes in [4] to simplify the hbmc-mux modelling   

[1] https://lore.kernel.org/all/76da0b98-3274-b047-db11-ecabc117ae11@ti.com/
[2] https://lore.kernel.org/all/20230510091850.28881-1-tony@atomide.com/
[3] https://lore.kernel.org/all/20230503115130.c7m4a7crub7kmfjw@gluten/
[4] https://lore.kernel.org/all/20230911151030.71100-1-afd@ti.com/

Nishanth Menon (2):
  arm64: dts: ti: k3-j7200-mcu-wakeup: Switch mcu_syscon to
    ti,j721e-system-controller
  arm64: dts: ti: k3-j7200-mcu-wakeup: Update fss node and hbmc_mux

 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)