From patchwork Mon Oct 9 08:24:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 13413073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEDC3E95A96 for ; Mon, 9 Oct 2023 08:25:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ljBsG7wEJdA6sv3GMHQzTOKg+ctrVNaA53g9DOhm5eI=; b=tEUSCleJJEDhlV NeQVT00Vb3nbMxFL5O0y4bVRwHRo50t4H9yRB3d2ypRDeN2cM5UwVswva5faW+N3UFK4zSamonlvH gv0a0cTDrRx9SA/1N4orHBDuko78Sz3vQDhSb08JELXh0T0SsFu9+TEBj3XPSaMlpHWQVN4l26RCo 1Ii2B5HKP2P5VcybhEgVmnNb7PSpBeqzinqMCObeciejquugXQ/tW3t0KBkI5rAiiSzOMNpM9rXrQ GrE810w/TU3tdjr2Wcp+p8Wq2dCvG/B93ZhP64XG7IZViRYsY4x8c1H6InwIyX4z6LlfPFX9LJE7+ OaF0XQfDrKLPGxrWs/nw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qplZe-009xq1-2f; Mon, 09 Oct 2023 08:25:10 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qplZW-009xny-0y for linux-arm-kernel@lists.infradead.org; Mon, 09 Oct 2023 08:25:06 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3998Os5B113187; Mon, 9 Oct 2023 03:24:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1696839894; bh=Tj7Gy6Xo6sZ11WWNP0dGT0Go1/OTwecYySniex9/ka0=; h=From:To:CC:Subject:Date; b=b9plz3cz3WsGh9Pl1ybaIf4nCkAm1CYMqxyZAy6uGKLiyGCK5D4h8Tvr9SmJhNGfV e9ySf0SfJAdU5hZMP2M13qPvsjTMCWMz3sL9uvVjwA+KPiZhyX8uHBgwsM9VdLr/f4 aNyybf3hleshU8qN5qy5lZn2+6OQMDoILB+Y912Q= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3998Ossx034359 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 9 Oct 2023 03:24:54 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 9 Oct 2023 03:24:54 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 9 Oct 2023 03:24:54 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3998Orre106452; Mon, 9 Oct 2023 03:24:53 -0500 From: Vaishnav Achath To: , , , , CC: , , , , , Subject: [PATCH v4 0/2] arm64: dts: ti: k3-j7200: Fixes for various dtbs_checks warnings Date: Mon, 9 Oct 2023 13:54:50 +0530 Message-ID: <20231009082452.30684-1-vaishnav.a@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231009_012502_441675_491A3011 X-CRM114-Status: GOOD ( 10.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Few fixups for j7200 dtbs_check warnings. This is V4 for the following series rebased and tested with 6.6-rc5, V3 : https://lore.kernel.org/all/20230513101343.785-1-vaishnav.a@ti.com V2 : https://lore.kernel.org/all/20230505115858.7391-1-vaishnav.a@ti.com/ V1 : https://lore.kernel.org/all/20230424173623.477577-1-nm@ti.com/ Bootlog with basic hyperflash testing (6.6.0-rc5-next-20231009): https://gist.github.com/vaishnavachath/f7265e932725fd992dbc4e48b993e9c0 Patch 2/2 depends on the following patch under review which enables reg-mux to be used when parent node is not syscon : https://lore.kernel.org/all/20230911151030.71100-1-afd@ti.com/ Changelog: V3->V4: * Rebase and tested with 6.6-rc5 V2->V3: * Drop pinctrl fix patch as the fix [2] is already merged to next. * Keep register regions unchanged as it is correct according to memory map, update commit message. V1->V2: * Address feedback as recommended in [3]. * Address feedback from Udit to limit the FSS register region size as per TRM. * Use reg-mux changes in [4] to simplify the hbmc-mux modelling [1] https://lore.kernel.org/all/76da0b98-3274-b047-db11-ecabc117ae11@ti.com/ [2] https://lore.kernel.org/all/20230510091850.28881-1-tony@atomide.com/ [3] https://lore.kernel.org/all/20230503115130.c7m4a7crub7kmfjw@gluten/ [4] https://lore.kernel.org/all/20230911151030.71100-1-afd@ti.com/ Nishanth Menon (2): arm64: dts: ti: k3-j7200-mcu-wakeup: Switch mcu_syscon to ti,j721e-system-controller arm64: dts: ti: k3-j7200-mcu-wakeup: Update fss node and hbmc_mux arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)