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Tue, 14 Nov 2023 13:57:14 GMT Received: from hyd-lablnx450.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 05:57:09 -0800 From: Bibek Kumar Patro To: , , , , , , , CC: , , , , , Bibek Kumar Patro Subject: [PATCH v2 0/3] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs Date: Tue, 14 Nov 2023 19:26:51 +0530 Message-ID: <20231114135654.30475-1-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MuRpWg32HSPcaImZL-FbIaTNgIIbirJ0 X-Proofpoint-GUID: MuRpWg32HSPcaImZL-FbIaTNgIIbirJ0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-14_12,2023-11-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 bulkscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1011 spamscore=0 mlxlogscore=790 phishscore=0 adultscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311140107 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231114_055727_983645_F3B4A0D8 X-CRM114-Status: GOOD ( 15.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch series consists of three parts and covers the following: 1. Introducing intital set of driver changes to implement ACTLR register for custom prefetcher settings in Qualcomm SoCs. 2. Adding ACTLR data and implementation operations for SM8550. 3. Re-enabling context caching for Qualcomm SoCs to retain prefetcher settings during reset and runtime suspend. Changes in v2 from v1: - Incorporated suggestions on v1 from Dmitry,Konrad,Pratyush. - Added defines for ACTLR values. - Linked sm8550 implementation structure to corresponding compatible string. - Repackaged actlr value set implementation to separate function. - Fixed indentation errors. - Link to v1: https://lore.kernel.org/all/20231103215124.1095-1-quic_bibekkum@quicinc.com/ Changes in v1 from RFC: - Incorporated suggestion form Robin on RFC. - Moved the actlr data table into driver, instead of maintaining it inside soc specific DT and piggybacking on exisiting iommus property (iommu = ) to set this value during smmu probe. - Link to RFC: //lore.kernel.org/all/a01e7e60-6ead-4a9e-ba90-22a8a6bbd03f@quicinc.com/ Bibek Kumar Patro (3): iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings iommu/arm-smmu: add ACTLR data and support for SM8550 iommu/arm-smmu: re-enable context caching in smmu reset operation drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 156 ++++++++++++++++++++- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 2 + drivers/iommu/arm/arm-smmu/arm-smmu.c | 5 +- drivers/iommu/arm/arm-smmu/arm-smmu.h | 5 + 4 files changed, 159 insertions(+), 9 deletions(-) --- 2.17.1