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Wysocki" , Viresh Kumar , Stephen Rothwell Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Brandon Cheo Fusi Subject: [RFC PATCH v2 0/3] Add support for reading D1 efuse speed bin Date: Thu, 21 Dec 2023 11:10:10 +0100 Message-Id: <20231221101013.67204-1-fusibrandon13@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231221_021041_123966_DE400014 X-CRM114-Status: GOOD ( 10.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi everyone, This series is an attempt to get feedback on decoding D1 efuse speed bins in the Sun50i H6 cpufreq driver, and turning the result into a meaningful value that selects voltage ranges in an OPP table. I want to make sure I get this right before sending in a v3 of the D1 cpufreq support series here https://lore.kernel.org/linux-sunxi/20231218110543.64044-1-fusibrandon13@gmail.com/T/#t which is currently stuck at https://lore.kernel.org/linux-sunxi/aad8302d-a015-44ee-ad11-1a4c6e00074c@sholland.org/ Changes in v2: - Make speed bin decoding generic in one patch and add D1 support in a separate patch - Fix OPP voltage ranges to avoid stability issues Brandon Cheo Fusi (3): cpufreq: sun50i: Refactor speed bin decoding cpufreq: sun50i: Add support for D1's speed bin decoding riscv: dts: allwinner: Fill in OPPs arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 19 +++- drivers/cpufreq/sun50i-cpufreq-nvmem.c | 89 +++++++++++++++---- 2 files changed, 89 insertions(+), 19 deletions(-)