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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id h10-20020a170902704a00b001d4816958c2sm8277113plt.166.2024.01.23.00.06.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 00:06:44 -0800 (PST) From: Jacky Huang To: linus.walleij@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, p.zabel@pengutronix.de, j.neuschaefer@gmx.net Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com Subject: [PATCH v3 0/4] Add support for nuvoton ma35d1 pin control Date: Tue, 23 Jan 2024 08:06:33 +0000 Message-Id: <20240123080637.1902578-1-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240123_000649_264548_489B9267 X-CRM114-Status: GOOD ( 14.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jacky Huang This patch series adds the pin control and GPIO driver for the nuvoton ma35d1 ARMv8 SoC. It includes DT binding documentation, the ma35d1 pin control driver, and device tree updates. This pin control driver has been tested on the ma35d1 som board with Linux 6.7. v3: - Update DTS and YAML files - Corrected the unit address of nodes gpioa ~ gpion. - Removed the invalid "pin-default" node. - Removed the phandle entry from "nuvoton,pins". - Update pinctrl driver - Fixed the Kconfig by using "depend on" instead of "if". - Removed unused #include of header files. - Utilized immutable irq_chip instead of dynamic irq_chip. - Replaced ma35_dt_free_map() with pinconf_generic_dt_free_map(). - Implemented other minor fixes as suggested by the reviewer. v2: - Update nuvoton,ma35d1-pinctrl.yaml - Update the 'nuvoton,pins' to follow the style of rockchip pinctrl approch. - Use power-source to indicate the pin voltage selection which follow the realtek pinctrl approch. - Instead of integer, use drive-strength-microamp to specify the real driving strength capability of IO pins. - Update ma35d1 pinctrl driver - Add I/O drive strength lookup table for translating device tree setting into control register. - Remove ma35d1-pinfunc.h which is unused after update definition of 'nuvoton,pins'. Jacky Huang (4): dt-bindings: reset: Add syscon to nuvoton ma35d1 system-management node dt-bindings: pinctrl: Document nuvoton ma35d1 pin control arm64: dts: nuvoton: Add pinctrl support for ma35d1 pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driver .../pinctrl/nuvoton,ma35d1-pinctrl.yaml | 163 ++ .../bindings/reset/nuvoton,ma35d1-reset.yaml | 3 +- .../boot/dts/nuvoton/ma35d1-iot-512m.dts | 80 +- .../boot/dts/nuvoton/ma35d1-som-256m.dts | 83 +- arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 150 +- drivers/pinctrl/nuvoton/Kconfig | 18 + drivers/pinctrl/nuvoton/Makefile | 2 + drivers/pinctrl/nuvoton/pinctrl-ma35.c | 1214 +++++++++++ drivers/pinctrl/nuvoton/pinctrl-ma35.h | 50 + drivers/pinctrl/nuvoton/pinctrl-ma35d1.c | 1797 +++++++++++++++++ 10 files changed, 3550 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35.c create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35.h create mode 100644 drivers/pinctrl/nuvoton/pinctrl-ma35d1.c