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Fri, 29 Mar 2024 21:07:06 GMT Received: from hu-c-gdjako-lv.qualcomm.com (10.49.16.6) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 29 Mar 2024 14:07:05 -0700 From: Georgi Djakov To: , , , CC: , , , , , , , , , , , , , , Subject: [PATCH v7 0/7] Add support for Translation Buffer Units Date: Fri, 29 Mar 2024 14:06:31 -0700 Message-ID: <20240329210638.3647523-1-quic_c_gdjako@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: WhE4aYoNGM6sQB3iEVDyUecjH7n6WqJW X-Proofpoint-GUID: WhE4aYoNGM6sQB3iEVDyUecjH7n6WqJW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-29_13,2024-03-28_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 impostorscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 phishscore=0 mlxlogscore=999 suspectscore=0 adultscore=0 priorityscore=1501 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403290188 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_140718_015532_B0DA75B3 X-CRM114-Status: GOOD ( 21.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The TCUs (Translation Control Units) and TBUs (Translation Buffer Units) are key components of the MMU-500. Multiple TBUs are connected to a single TCU over an interconnect. Each TBU contains a TLB that caches page tables. The MMU-500 implements a TBU for each connected master, and the TBU is designed, so that it is local to the master. A common TBU DT schema is added to describe the TBUs. The Qualcomm SDM845 and SC7280 platforms have an implementation of the SMMU-500, that has multiple TBUs. A vendor-specific DT schema is added to describe the resources for each TBU (register space, power-domains, interconnects and clocks). The TBU driver will manage the resources and allow the system to operate the TBUs during a context fault to obtain details by doing s1 inv, software + hardware page table walks etc. This is implemented with ATOS/eCATs as the ATS feature is not supported. Being able to query the TBUs is useful for debugging various hardware/software issues on these platforms. v7: - Pick Reviewed-by for the DT binding (Rob) - Don't spam the log if the dts changes are not there (Konrad) v6: https://lore.kernel.org/r/20240307190525.395291-1-quic_c_gdjako@quicinc.com/ - Use SoC-specific compatibles (Krzysztof) - Use additionalProperties: false (Krzysztof) - Wrap description text to 80 cols (Krzysztof) v5: https://lore.kernel.org/r/20240226172218.69486-1-quic_c_gdjako@quicinc.com - Drop the common TBU bindings and child nodes. These TBU functionalities are only Qualcomm specific and not generic. In the unmodified ARM MMU-500 implementation there are no TBU-specific resources, so just make them standalone DT nodes. (Robin) - The "qcom,stream-id-range" DT property now takes a phandle to the smmu and a stream ID range. v4: https://lore.kernel.org/r/20240201210529.7728-1-quic_c_gdjako@quicinc.com/ - Create a common TBU schema. Move the vendor-specific properties into a separate schema that references the common one. (Rob) - Drop unused DT labels in example, fix regex. (Rob) - Properly rebase on latest code. v3: https://lore.kernel.org/r/20231220060236.18600-1-quic_c_gdjako@quicinc.com - Having a TBU is not Qualcomm specific, so allow having TBU child nodes with no specific constraints on properties. For some of the vendor compatibles however, add a schema to describe specific properties and allow validation. (Rob) - Drop the useless reg-names DT property on TBUs. (Rob) - Make the stream-id-range DT property a common one. (Rob) - Fix the DT example. (Rob) - Minor fixes on the TBU driver. - Add support for SC7280 platforms. v2: https://lore.kernel.org/r/20231118042730.2799-1-quic_c_gdjako@quicinc.com - Improve DT binding description, add full example. (Konrad) - Drop Qcom specific stuff from the generic binding. (Rob) - Unconditionally try to populate subnodes. (Konrad) - Improve TBU driver commit text, remove memory barriers. (Bjorn) - Move TBU stuff into separate file. Make the driver builtin. - TODO: Evaluate whether to keep TBU support as a separate driver or just instantiate things from qcom_smmu_impl_init() v1: https://lore.kernel.org/r/20231019021923.13939-1-quic_c_gdjako@quicinc.com Georgi Djakov (7): dt-bindings: iommu: Add Qualcomm TBU iommu/arm-smmu-qcom-tbu: Add Qualcomm TBU driver iommu/arm-smmu: Allow using a threaded handler for context interrupts iommu/arm-smmu-qcom: Use a custom context fault handler for sdm845 arm64: dts: qcom: sdm845: Add DT nodes for the TBUs iommu/arm-smmu-qcom: Use the custom fault handler on more platforms arm64: dts: qcom: sc7280: Add DT nodes for the TBUs .../devicetree/bindings/iommu/qcom,tbu.yaml | 69 +++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 89 +++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 70 +++ drivers/iommu/Kconfig | 9 + drivers/iommu/arm/arm-smmu/Makefile | 1 + .../iommu/arm/arm-smmu/arm-smmu-qcom-tbu.c | 515 ++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 8 + drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 2 + drivers/iommu/arm/arm-smmu/arm-smmu.c | 12 +- drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 + 10 files changed, 776 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/iommu/qcom,tbu.yaml create mode 100644 drivers/iommu/arm/arm-smmu/arm-smmu-qcom-tbu.c