| Message ID | 20240411130150.128107-1-cassel@kernel.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | rockchip pcie3-phy separate refclk support | expand |
Hi Niklas, On 11-04-24, 15:01, Niklas Cassel wrote: > This series is based on: linux-phy phy/fixes > (Since there are other rockchip,pcie3-phy changes there that have not > yet reached mainline and which would otherwise have caused conflicts.) I merged the fixes into next and tried to apply this patch but second one fails for me. I guess it needs to be rebased. Always based these changes on phy/next or phy/fixes+next (which is what I will end up with to resolve)
On Fri, Apr 12, 2024 at 03:03:59PM +0530, Vinod Koul wrote: > Hi Niklas, > > On 11-04-24, 15:01, Niklas Cassel wrote: > > This series is based on: linux-phy phy/fixes > > (Since there are other rockchip,pcie3-phy changes there that have not > > yet reached mainline and which would otherwise have caused conflicts.) > > I merged the fixes into next and tried to apply this patch but second > one fails for me. I guess it needs to be rebased. > > Always based these changes on phy/next or phy/fixes+next (which is what > I will end up with to resolve) I based it on phy/fixes since there were commits for this driver in phy/fixes that were not in phy/next, so I did it for you to not get conflicts :) Since this still gave you conflicts, there must have been other changes in phy/next for this driver. I must have missed that, sorry. I see that you have now merged phy/fixes into phy/next, that will make things easier, thank you. I will send out a V2 based on phy/next shortly. Kind regards, Niklas
On Thu, 11 Apr 2024 15:01:46 +0200, Niklas Cassel wrote: > This series is based on: linux-phy phy/fixes > (Since there are other rockchip,pcie3-phy changes there that have not > yet reached mainline and which would otherwise have caused conflicts.) > > Hello all, > > The rockchip,pcie3-phy PHY in rk3588 is by default configured to run in > "common reference clock" mode. (Which is a sensible default, as the most > commonly used clock configuration is "common reference clock".) > > [...] Applied, thanks! [1/2] dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-mode commit: 46492d10067660785a09db4ce9244545126a17b8 [2/2] phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode commit: a1fe1eca0d8be69ccc1f3d615e5a529df1c82e66 Best regards,
This series is based on: linux-phy phy/fixes (Since there are other rockchip,pcie3-phy changes there that have not yet reached mainline and which would otherwise have caused conflicts.) Hello all, The rockchip,pcie3-phy PHY in rk3588 is by default configured to run in "common reference clock" mode. (Which is a sensible default, as the most commonly used clock configuration is "common reference clock".) However, PCIe also defines two other configurations where the Root Complex and Endpoint uses separate reference clocks: SRNS and SRIS. Having the Root Complex PHY configured in "common reference clock mode" while having an Endpoint connected which is supplying its own reference clock (i.e. SRNS or SRIS configuration), will either result in the link training failing, or a highly unstable link that continuously jumps between link states L0 and recovery. Add a rockchip specific device tree property that can be added to the rk3588 Root Complex device tree PHY node, if the connected Endpoint device is using a separate refererence clock. This way we will get a stable link when using an Endpoint configured in SRNS or SRIS mode. Kind regards, Niklas Niklas Cassel (2): dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-mode phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode .../bindings/phy/rockchip,pcie3-phy.yaml | 10 +++++ .../phy/rockchip/phy-rockchip-snps-pcie3.c | 37 +++++++++++++++++++ 2 files changed, 47 insertions(+)