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[v3,0/3] Add PCIe DT support for TI's J784S4 SoC

Message ID 20240523111008.4057988-1-s-vadapalli@ti.com (mailing list archive)
Headers show
Series Add PCIe DT support for TI's J784S4 SoC | expand

Message

Siddharth Vadapalli May 23, 2024, 11:10 a.m. UTC 
TI's J784S4 has two x4 Lane and two x2 Lane Gen3 PCIe Controllers.
This series adds the device-tree nodes for all 4 PCIe instances in the
SoC file. The Board (J784S4-EVM) has only PCIe0 and PCIe1 instances of
PCIe brought out, due to which only those PCIe instances are being
enabled in the board file. The device-tree overlay to enable PCIe0 and
PCIe1 in Endpoint mode of operation is also included in this series.

v2:
https://lore.kernel.org/r/20240520101149.3243151-1-s-vadapalli@ti.com/
Changes since v2:
- Rebased on linux-next tagged next-20240523.
- Based on feedback from Francesco Dolcini <francesco@dolcini.it> at:
  https://lore.kernel.org/r/20240521200909.GA3707@francesco-nb/
  the device-tree nodes for PCIe2 and PCIe3 instances of PCIe have been
  added.

v1:
https://lore.kernel.org/r/20240129114749.1197579-1-s-vadapalli@ti.com
Changes since v1:
- Rebased series on linux-next tagged next-20240520.
- All dependencies mentioned in v1 series have been met. This series has
  no further dependencies for functionality.
- Added "pcie0_ctrl" and "pcie1_ctrl" nodes within the System Controller
  node (scm_conf). This enables reusing the existing
  "ti,syscon-pcie-ctrl" property without having to map the entire System
  Controller region for configuring the PCIe specific registers within
  "scm_conf". This change is also done in the "overlay" file in patch
  3/3 w.r.t. providing the phandle to the pcie0_ctrl and pcie1_ctrl
  nodes to the "ti,syscon-pcie-ctrl" property in the overlay.

Logs:
https://gist.github.com/Siddharth-Vadapalli-at-TI/cbf5255b72d7805e86331150a8b2b5c5

Regards,
Siddharth.

Siddharth Vadapalli (3):
  arm64: dts: ti: k3-j784s4-main: Add PCIe nodes
  arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode
  arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode

 arch/arm64/boot/dts/ti/Makefile               |   7 +-
 .../dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso  |  79 ++++++++++
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts      |  46 ++++++
 arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi    | 136 ++++++++++++++++++
 4 files changed, 267 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso

Comments

Siddharth Vadapalli May 28, 2024, 8:56 a.m. UTC | #1 
On Thu, May 23, 2024 at 04:40:05PM +0530, Siddharth Vadapalli wrote:
> TI's J784S4 has two x4 Lane and two x2 Lane Gen3 PCIe Controllers.
> This series adds the device-tree nodes for all 4 PCIe instances in the
> SoC file. The Board (J784S4-EVM) has only PCIe0 and PCIe1 instances of
> PCIe brought out, due to which only those PCIe instances are being
> enabled in the board file. The device-tree overlay to enable PCIe0 and
> PCIe1 in Endpoint mode of operation is also included in this series.

Kindly ignore this series. I will post the v4 series with PCIe2 and
PCIe3 regions reserved in k3-j784s4.dtsi which I have missed in this
series.

Regards,
Siddharth.