From patchwork Thu May 23 11:10:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13671627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21578C25B75 for ; Thu, 23 May 2024 11:10:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=WTOqp57yOO/iVACpZuzJPs8ePR1Xyyp46/yl+Vh6RYE=; b=P5BpDQxAwjxCKI QgLf5Y1ztXN/IBR91855fTCQey4H/oLm5R9A7cekeM8HMOTity1nPgE44BEBZkxGAuh2rRH0qHBlu Rjx6OWfwEENRFQPSIwCCHTbYUc4iZUhh7ksJuTn2ed/aTFBc1lfNGJY7JWZ/3DkFOLcwVf9KNIZYa 65WMx2FnxKNLCl9JasG9KwzKjV/Q/aGSnEsocne+q1KqB2hzWulIvBjbsTAdt1UdOUpxKbCh1obcx YbdVPUQAXas6g0r04vBQ0XnBl+3SZR4IKz1gUr7sCls0QlsCcLUrwCt7QmD/z7XYPPL2D1Epx9FVr cb3SIaHF5gwBcjaeA8eQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sA6L9-00000005zLd-0xMh; Thu, 23 May 2024 11:10:31 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sA6L4-00000005zJw-3pPK for linux-arm-kernel@lists.infradead.org; Thu, 23 May 2024 11:10:29 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 44NBAEJE087367; Thu, 23 May 2024 06:10:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1716462614; bh=IhXMjns6cBU5P/4SY9BY7kWj8Gws83AomFhTo1xso74=; h=From:To:CC:Subject:Date; b=dawR48G5/IdVAbp7t2C1NwLtFtSTHGreZmDJIXGpJXInhyzhRti1yExL7+jMIKPDd MKJCcvsmSVNDdfQKTSo9D3l2AowebiQI5Lw6QAhl1bnXm1tNnmP4CQlJE+hx3jW3dU pEn9yfnxlT+OnlHJvQVVYQmCzU8NaoGZOBJcapqc= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 44NBAED7051169 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 23 May 2024 06:10:14 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 23 May 2024 06:10:13 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 23 May 2024 06:10:13 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44NBA9Ea082115; Thu, 23 May 2024 06:10:10 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , , Subject: [PATCH v3 0/3] Add PCIe DT support for TI's J784S4 SoC Date: Thu, 23 May 2024 16:40:05 +0530 Message-ID: <20240523111008.4057988-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240523_041027_273778_79B7C765 X-CRM114-Status: GOOD ( 12.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org TI's J784S4 has two x4 Lane and two x2 Lane Gen3 PCIe Controllers. This series adds the device-tree nodes for all 4 PCIe instances in the SoC file. The Board (J784S4-EVM) has only PCIe0 and PCIe1 instances of PCIe brought out, due to which only those PCIe instances are being enabled in the board file. The device-tree overlay to enable PCIe0 and PCIe1 in Endpoint mode of operation is also included in this series. v2: https://lore.kernel.org/r/20240520101149.3243151-1-s-vadapalli@ti.com/ Changes since v2: - Rebased on linux-next tagged next-20240523. - Based on feedback from Francesco Dolcini at: https://lore.kernel.org/r/20240521200909.GA3707@francesco-nb/ the device-tree nodes for PCIe2 and PCIe3 instances of PCIe have been added. v1: https://lore.kernel.org/r/20240129114749.1197579-1-s-vadapalli@ti.com Changes since v1: - Rebased series on linux-next tagged next-20240520. - All dependencies mentioned in v1 series have been met. This series has no further dependencies for functionality. - Added "pcie0_ctrl" and "pcie1_ctrl" nodes within the System Controller node (scm_conf). This enables reusing the existing "ti,syscon-pcie-ctrl" property without having to map the entire System Controller region for configuring the PCIe specific registers within "scm_conf". This change is also done in the "overlay" file in patch 3/3 w.r.t. providing the phandle to the pcie0_ctrl and pcie1_ctrl nodes to the "ti,syscon-pcie-ctrl" property in the overlay. Logs: https://gist.github.com/Siddharth-Vadapalli-at-TI/cbf5255b72d7805e86331150a8b2b5c5 Regards, Siddharth. Siddharth Vadapalli (3): arm64: dts: ti: k3-j784s4-main: Add PCIe nodes arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode arch/arm64/boot/dts/ti/Makefile | 7 +- .../dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 79 ++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 46 ++++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 136 ++++++++++++++++++ 4 files changed, 267 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso