From patchwork Fri May 24 09:05:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13672882 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6049C25B7D for ; Fri, 24 May 2024 09:06:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=mms5PhMZ0QpelWRWyfSezo579qVG8I9Yx8MUB1KgUzA=; b=a6zhtYWZsKp6gL MvNUPsG0I7uRD4XRr4jjqh6YnynCIwupr1ckH8vrr1+S59jX623IT+Y4kXkDz/YZEpgF4+ZDgQUJ6 YWiBdYslMAG443Cd67P2W4sM0uqWWejXOWQydLHseCPkG/7JDzk7NqSBCg0uQxZ0PY0JnEU4BfYLV 8HrKU1Y27sNU29QHkHeHWzkQk305jBBuQ07eAn/EDk0u1JHBfmI/mY3+VRz7lYLcrtq861G0TH8p3 k+1hcYtJBCmVOsNsYk72ZW/5ajd4vX7PGRHS+HNvt04a3xDE1xm2bGBgshoSjVbBY7143nHKddozv mLY4O6CUbMi3QfsWbu/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sAQsF-00000008TcM-2tBM; Fri, 24 May 2024 09:06:03 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sAQrh-00000008TFG-0qpF for linux-arm-kernel@lists.infradead.org; Fri, 24 May 2024 09:05:35 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 44O95K8m071471; Fri, 24 May 2024 04:05:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1716541520; bh=ERdEWnZaf8wEUS9yivBfRntCDoHPogtyIgugw5XQBgc=; h=From:To:CC:Subject:Date; b=nQ8LxpPiJVzvV6eCpzfGnAjTwECW/tyi3KUurUc5i/IvuLvrsN4bjE5+GSxt6X8e4 UygUl+hx/uBm+JV53cVSxT/AztzzIBRurI+yrKUL34kfDLZTbM2goxA7Rjb8u4+QdT pqZSarm40pIjE9RIWefO6o0kaRW/BPTyThQqQPsc= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 44O95KCR029558 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 May 2024 04:05:20 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 24 May 2024 04:05:19 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 24 May 2024 04:05:19 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44O95F7F017455; Fri, 24 May 2024 04:05:15 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v3 0/7] Add PCIe and USB device-tree support for J722S Date: Fri, 24 May 2024 14:35:07 +0530 Message-ID: <20240524090514.152727-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240524_020529_770490_4C17E102 X-CRM114-Status: GOOD ( 18.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, This series adds device-tree support for PCIe and USB on J722S SoC. This series is the v3 for the v2 USB series at: https://lore.kernel.org/r/20240513114443.16350-1-r-gunasekaran@ti.com/ and is also the v1 series for enabling PCIe device-tree support for J722S. Since the v2 USB series combined portions of the PCIe changes incorrectly, I have updated this series to contain USB specific changes in the first 3 patches of this series while moving the PCIe specific changes to the remaining 4 patches in this series. Series is based on linux-next tagged next-20240524. v2 for USB: https://lore.kernel.org/r/20240513114443.16350-1-r-gunasekaran@ti.com/ Changes since v2 USB series: - For patch 1: => Renamed serdes0_ln_ctrl to serdes_ln_ctrl to keep the format consistent across SoCs where a single node is sufficient to represent the Lane-Muxing for all instances of the Serdes. - For patch 2: => No changes since v2. - For patch 3: => Renamed serdes0_ln_ctrl to serdes_ln_ctrl corresponding to the change made in patch 1. => Dropped Serdes1 idle-states since it has not yet been added in the serdes_ln_ctrl node. => Dropped Serdes1 specific Lane-Muxing macros in "k3-serdes.h". => Added newline after /* J722S */ in "k3-serdes.h" following the file convention. v1 for USB: https://lore.kernel.org/r/20240429120932.11456-1-r-gunasekaran@ti.com/ Changes since v1 USB series: - Introduced k3-j722s-main.dtsi newly to add the main domain peripherals that are present additionally in J722S as suggested by Andrew Davis. - Used generic node names as suggested by Roger Quadros. - Removed the aliases for usb as suggested by Rob Herring. This series has no dependencies and has been tested on J722S-EVM. Logs testing PCIe functionality with an NVMe SSD connected to the J722S-EVM and testing USB functionality limited to "lsusb" output: https://gist.github.com/Siddharth-Vadapalli-at-TI/6a9cdcec24add0114e63db736b3e23fb Regards, Siddharth. Ravi Gunasekaran (3): arm64: dts: ti: k3-j722s-main: Add support for SERDES0 arm64: dts: ti: k3-j722s-main: Redefine USB1 node description arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1 Siddharth Vadapalli (4): arm64: dts: ti: k3-serdes: Add Serdes1 lane-muxing macros for J722S arm64: dts: ti: k3-j722s: Add lane mux for Serdes1 arm64: dts: ti: k3-j722s-main: Add WIZ1 and Serdes1 nodes arm64: dts: ti: k3-j722s: Add support for PCIe0 arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 72 +++++++++ arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 177 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 5 + arch/arm64/boot/dts/ti/k3-serdes.h | 8 + 4 files changed, 262 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi