From patchwork Wed May 29 17:21:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13679317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C49FBC41513 for ; Wed, 29 May 2024 17:21:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=6EE/KWGwcZmqnJo0kezWUiWQ23+LC4MMiEgu5+ovZHE=; b=BTEEdCOjUquAJQ A/EM+0AGI6++5p7KAdXMZ15cXZ6IjY4zVWysk66yNr50Ton/DkmNHJVGAJ7O3OpzCXbXeHonIdWNm edjCK90KpmAbw/9a1Q/hIsfMQimsKN/jQJLufRQz+Fum5e2eAn8MxR/kjqtrQIfYreorFy/1WQOfO gGlDFbFJl1qXyprdhE/JUBsTh+zeN7O/yrM0AZXJGRUmdlCrIBDv8EzxBoldx1oqYtXfnM2Gm7fxU QQ/IRnwEl7maXa7GHP3PG4v2W1oLtdShw5myJfABXo/D1fI1KDvKqr3x6XpveGJx0NUTxWaJYmwNx sP/cI/ulOmdd0Qr0mTYQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sCMzO-000000053cf-2NBk; Wed, 29 May 2024 17:21:26 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sCMzK-000000053Zs-392Z for linux-arm-kernel@lists.infradead.org; Wed, 29 May 2024 17:21:24 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 24918339; Wed, 29 May 2024 10:21:45 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 09A423F792; Wed, 29 May 2024 10:21:19 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: alexandru.elisei@arm.com, catalin.marinas@arm.com, mark.rutland@arm.com, maz@kernel.org, will@kernel.org Subject: [PATCH 0/4] irqchip/gic-v3: use compiletime constant PMR values Date: Wed, 29 May 2024 18:21:12 +0100 Message-Id: <20240529172116.1313498-1-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240529_102122_932902_F1D667F1 X-CRM114-Status: GOOD ( 18.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The GIC distributor and PMR/RPR can present different views of the interrupt priority space dependent upon the values of GICD_CTLR.DS and SCR_EL3.FIQ. Currently we treat the distributor's view of the priority space as canonical, and when the two differ we change the way we handle values in the PMR/RPR, using the `gic_nonsecure_priorities` static key to decide what to do. This approach works, but it's sub-optimal. When using pseudo-NMI we manipulate the distributor rarely, and we manipulate the PMR/RPR registers very frequently in code spread out throughout the kernel (e.g. local_irq_{save,restore}()). It would be nicer if we could use fixed values for the PMR/RPR, and dynamically choose the values programmed into the distributor. This series reworks the GIC code (and a small part of arm64 architecture code) to allow the use of compiletime-constant PMR values. This simplifies the logic for PMR management, and when using pseudo-NMI this results in smaller and better generates code for saving/restoring the irqflags, saving ~4K of text for defconfig + CONFIG_PSEUDO_NMI=y. The first patch is a preparatory cleanup which I think makes sense regardlesss of the rest of the series. The second and third patches rework the GICv3 code to be able to choose priorities at boot time, and the final patch makes the actual switch. I've given this some light testing atop v6.10-rc1 with pseudo-NMI enabled (with priority debugging), along with lockdep on the following systems: * M1SDP Morello board, bare metal Where GICD_CTRL.DS=0, SCR_EL3.FIQ=0 Using shifted (NS) values in the distributor * M1SDP Morello board, KVM guest Where GICD_CTRL.DS=1, SCR_EL3.FIQ=0 Using unshifted values in the distributor * ThunderX2, KVM guest Where GICD_CTRL.DS=1, SCR_EL3.FIQ=0 Using unshifted values in the distributor On ThunderX2 bare-metal there is an existing boot-time hang when using pseudo-NMI which is not solved by this series. With this seires applied, the logging added in patch 3 reports that GICD_CTRL.DS=1, SCR_EL3.FIQ=0, and so this should be using the same priorities which are seem to work in a guest. Mark. Mark Rutland (4): irqchip/gic-common: remove sync_access callback irqchip/gic-v3: make distributor priorities variables irqchip/gic-v3: detect GICD_CTRL.DS and SCR_EL3.FIQ earlier irqchip/gic-v3: select priorities at boot time arch/arm64/include/asm/arch_gicv3.h | 15 -- arch/arm64/include/asm/ptrace.h | 35 +--- arch/arm64/kernel/image-vars.h | 5 - drivers/irqchip/irq-gic-common.c | 22 +-- drivers/irqchip/irq-gic-common.h | 7 +- drivers/irqchip/irq-gic-v3-its.c | 11 +- drivers/irqchip/irq-gic-v3.c | 225 ++++++++++++------------ drivers/irqchip/irq-gic.c | 10 +- drivers/irqchip/irq-hip04.c | 6 +- include/linux/irqchip/arm-gic-common.h | 4 - include/linux/irqchip/arm-gic-v3-prio.h | 52 ++++++ include/linux/irqchip/arm-gic-v3.h | 2 +- 12 files changed, 193 insertions(+), 201 deletions(-) create mode 100644 include/linux/irqchip/arm-gic-v3-prio.h Reviewed-by: Marc Zyngier Tested-by: Marc Zyngier