From patchwork Tue Jun 4 08:52:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13684902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4FC3C25B7E for ; Tue, 4 Jun 2024 08:53:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=9Mi3zUQus9Asi4QdkyG0LY4UfkcPGC7ybTTAd2nP+yo=; b=XujkmzUNQmEYXi i9oMD/rwsKI+dBpMGg6K5qtZfVOCXgSSB1rLPBswe/7XRdFg+dQg5q8NUWAVw/Xr/Dbx6HcKcHHsz NEsdbfBWGu3GMx6j2/XCCZRVH7l/KdPEBM/By9fdqttQ7Siljr5zNKCrp2NumtYQDS+dzgtDOp1+/ 6bHZa/Ja9c+4X7r41dTjex7hgxMQoYxV4p9cblWEiD6wQ5TKulG8iRymsDS3gtYHJ7txmYJzLyxvQ j46oCjTH5aDRJMf54A+/xoX2Se81YI3od+oNtYk5nmz8HaU8SEwI5HUk3IAVYBX8oD9zm+ipIOLpe IYiXkt1ixsbZaJ0Srf4A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sEPup-00000001kCD-0Jnn; Tue, 04 Jun 2024 08:53:11 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sEPum-00000001kAZ-05eS for linux-arm-kernel@lists.infradead.org; Tue, 04 Jun 2024 08:53:09 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 4548qvv1104969; Tue, 4 Jun 2024 03:52:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1717491177; bh=6iyLsfE5NFGLIDenSZ7LevfQ5SYEgR7vWcrXflvbod0=; h=From:To:CC:Subject:Date; b=QcfbN6qaz7Gbahay7n3vesS7D/GPGHdB11dY6QcJXvb7IT2cjvdbRUMAJKOAHB29N e1NskZl4SEC5dR9b2ZSbJxsMZKPj5tnCKjMsv9uOMEMAZAseYXwCyIwbpuKi8Gmtcl oa5wkOOBtFXsaN5BaEW9cYYcUKxn2GcFWGYo30ow= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 4548qvaL083479 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2024 03:52:57 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 4 Jun 2024 03:52:57 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 4 Jun 2024 03:52:57 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4548qqQh066926; Tue, 4 Jun 2024 03:52:53 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v5 0/7] Add PCIe, SERDES and USB DT support for J722S Date: Tue, 4 Jun 2024 14:22:45 +0530 Message-ID: <20240604085252.3686037-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240604_015308_276594_B2F0F0F5 X-CRM114-Status: GOOD ( 16.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, This series adds the device-tree support for enabling PCIe and USB functionality on J722S-EVM. Since AM62P and J722S SoCs share most of the peripherals, the files have been renamed to indicate the same. The main domain peripherals on both SoCs that aren't shared are present in the "soc-main.dtsi" files. This change has been made based on Roger's feedback at: https://lore.kernel.org/r/f52d9569-a399-422f-9cf0-b0bf69b64d18@kernel.org/ This series has been tested on J722S-EVM for PCIe and USB functionality: https://gist.github.com/Siddharth-Vadapalli-at-TI/02c037efd3666ea8232d7bb8b0fa42f3 Sanity testing on AM62P5-SK with this series: https://gist.github.com/Siddharth-Vadapalli-at-TI/1fb178f31b7cbc8eefd424e1e540ef3b v4: https://lore.kernel.org/r/20240601121554.2860403-1-s-vadapalli@ti.com/ Changes since v4: - Rebased series on linux-next tagged next-20240604. - Based on Andrew's feedback at: https://lore.kernel.org/r/086fa11e-10f8-463d-8966-1a33a52a3146@ti.com/ MCU was retained as-is while main and wakeup were changed to MAIN and WAKEUP in the respective shared files. Also, newline was added between the file description and the Copyright in all the files. Collected Acked-by tag for the 1st patch since these changes have been made. - Based on Andrew's feedback at: https://lore.kernel.org/r/147d58a6-0cad-47b6-a069-755f835a77e9@ti.com/ SERDES1 has also been disabled in k3-j722s-main.dtsi similar to SERDES0. - Based on Andrew's feedback at: https://lore.kernel.org/r/183a9d15-939e-433b-84ba-8a64eb8ef3ec@ti.com/ the `status = "okay";` line has been moved to the end of the `pcie0_rc` node referenced in k3-j722s-evm.dts following the updated ordering rules. Also, the SERDES1 node has been enabled in the k3-j722s-evm.dts file since it has been disabled in the k3-j722s-main.dtsi file. Regards, Siddharth. Siddharth Vadapalli (7): arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to am62p-main.dtsi arm64: dts: ti: k3-j722s: Add main domain peripherals specific to J722S arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common.dtsi arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM .../dts/ti/k3-am62p-j722s-common-main.dtsi | 1068 +++++++++++++++++ ...cu.dtsi => k3-am62p-j722s-common-mcu.dtsi} | 3 +- ...dtsi => k3-am62p-j722s-common-wakeup.dtsi} | 3 +- ...-am62p.dtsi => k3-am62p-j722s-common.dtsi} | 6 +- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 1063 +--------------- arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 3 +- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 73 ++ arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 173 +++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 97 +- arch/arm64/boot/dts/ti/k3-serdes.h | 8 + 10 files changed, 1429 insertions(+), 1068 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi rename arch/arm64/boot/dts/ti/{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi} (98%) rename arch/arm64/boot/dts/ti/{k3-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} (97%) rename arch/arm64/boot/dts/ti/{k3-am62p.dtsi => k3-am62p-j722s-common.dtsi} (97%) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi