[v2,00/16] coresight: Use per-sink trace ID maps for Perf sessions

Message

James Clark June 4, 2024, 2:30 p.m. UTC

This will allow sessions with more than CORESIGHT_TRACE_IDS_MAX ETMs
as long as there are fewer than that many ETMs connected to each sink.

Each sink owns its own trace ID map, and any Perf session connecting to
that sink will allocate from it, even if the sink is currently in use by
other users. This is similar to the existing behavior where the dynamic
trace IDs are constant as long as there is any concurrent Perf session
active. It's not completely optimal because slightly more IDs will be
used than necessary, but the optimal solution involves tracking the PIDs
of each session and allocating ID maps based on the session owner. This
is difficult to do with the combination of per-thread and per-cpu modes
and some scheduling issues. The complexity of this isn't likely to worth
it because even with multiple users they'd just see a difference in the
ordering of ID allocations rather than hitting any limits (unless the
hardware does have too many ETMs connected to one sink).

Per-thread mode works but only until there are any overlapping IDs, at
which point Perf will error out. Both per-thread mode and sysfs mode are
left to future changes, but both can be added on top of this initial
implementation and only sysfs mode requires further driver changes.

The HW_ID version field hasn't been bumped in order to not break Perf
which already has an error condition for other values of that field.
Instead a new minor version has been added which signifies that there
are new fields but the old fields are backwards compatible.

Changes since V1:

 * Rename coresight_device.perf_id_map to perf_sink_id_map.
 * Instead of outputting a HW_ID for each reachable ETM, output
   the sink ID and continue to output only the HW_ID once for
   each mapping.
 * Keep the first two Perf patches so that it applies cleanly
   on coresight-next, although they have been applied on perf-tools-next
 * Add new *_map() functions to the trace ID public API instead of
   modifying existing ones.
 * Collapse "coresight: Pass trace ID map into source enable" into
   "coresight: Use per-sink trace ID maps for Perf sessions" because the
   first commit relied on the default map being accessible which is no
   longer necessary due to the previous bullet point.

James Clark (16):
  perf cs-etm: Print error for new PERF_RECORD_AUX_OUTPUT_HW_ID versions
  perf auxtrace: Allow number of queues to be specified
  perf: cs-etm: Create decoders after both AUX and HW_ID search passes
  perf: cs-etm: Allocate queues for all CPUs
  perf: cs-etm: Move traceid_list to each queue
  perf: cs-etm: Create decoders based on the trace ID mappings
  perf: cs-etm: Support version 0.1 of HW_ID packets
  coresight: Remove unused ETM Perf stubs
  coresight: Clarify comments around the PID of the sink owner
  coresight: Move struct coresight_trace_id_map to common header
  coresight: Expose map arguments in trace ID API
  coresight: Make CPU id map a property of a trace ID map
  coresight: Use per-sink trace ID maps for Perf sessions
  coresight: Remove pending trace ID release mechanism
  coresight: Re-emit trace IDs when the sink changes in per-thread mode
  coresight: Emit sink ID in the HW_ID packets

 drivers/hwtracing/coresight/coresight-core.c  |  36 +-
 drivers/hwtracing/coresight/coresight-dummy.c |   3 +-
 .../hwtracing/coresight/coresight-etm-perf.c  |  50 +-
 .../hwtracing/coresight/coresight-etm-perf.h  |  20 +-
 .../coresight/coresight-etm3x-core.c          |   9 +-
 .../coresight/coresight-etm4x-core.c          |   9 +-
 drivers/hwtracing/coresight/coresight-priv.h  |   1 +
 drivers/hwtracing/coresight/coresight-stm.c   |   3 +-
 drivers/hwtracing/coresight/coresight-sysfs.c |   3 +-
 .../hwtracing/coresight/coresight-tmc-etr.c   |   5 +-
 drivers/hwtracing/coresight/coresight-tmc.h   |   5 +-
 drivers/hwtracing/coresight/coresight-tpdm.c  |   3 +-
 .../hwtracing/coresight/coresight-trace-id.c  | 109 ++--
 .../hwtracing/coresight/coresight-trace-id.h  |  70 +-
 include/linux/coresight-pmu.h                 |  17 +-
 include/linux/coresight.h                     |  20 +-
 tools/include/linux/coresight-pmu.h           |  17 +-
 tools/perf/util/auxtrace.c                    |   9 +-
 tools/perf/util/auxtrace.h                    |   1 +
 .../perf/util/cs-etm-decoder/cs-etm-decoder.c |  28 +-
 tools/perf/util/cs-etm.c                      | 603 ++++++++++++------
 tools/perf/util/cs-etm.h                      |   2 +-
 22 files changed, 628 insertions(+), 395 deletions(-)

Comments

Leo Yan June 5, 2024, 8:35 p.m. UTC | #1

On 6/4/24 15:30, James Clark wrote:
> This will allow sessions with more than CORESIGHT_TRACE_IDS_MAX ETMs
> as long as there are fewer than that many ETMs connected to each sink.

I tested this patch set on Hikey960 with below combinations:

- Only applied the kernel patches;
- Only applied the perf tool patches;
- Applied both the kernel and perf tool patches.

All of them can pass the test for `perf record` and `perf report` 
commands, I think this patch series is promised on Armv8 platform with 
small amount of CPUs.

Tested-by: Leo Yan <[e-mail]>

As you said that there might be a concern for running this patch set on 
a system with big amount of CPUs. Once you think it's ready for merging, 
please share at here.

Thanks,
Leo