From patchwork Mon Jul 29 04:36:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13744348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6CEC6C3DA61 for ; Mon, 29 Jul 2024 04:36:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=XjA8aqUcxLYUyOEcXETT85R4pwY5lJgM6jQUjA7UzU0=; b=Yf7icamfprs7e363je8XHLCvMK HGkQwjjHXjWl3BXE9GJzWUGlxEO8kuEqcCufZz9jXtdlCsQNZcyQZkBvattSQgfzahm5Tq00yG9su cPgCpGibwvolgz5WCjurgKk8z7bO2Uscb67GBhlms0Gt70mpNoLItUBDHrGNanshRqVPLkj0awv8Q owWdQmQ3wXAWlFiv7O5QoarZCS7gE5VEaFNr7ameQdIou8cc2Qqz9I469ld3IjbkC/O5CzNcyO3rF YaHxiGguzc22mLvrvhWcIf+9+LnJufgEd4PnfjFsRldh96sk/dQ8ShLhGLex5nNwCHvQDlcZutCHZ hhvGjkeg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYI7u-00000009xuw-1WJr; Mon, 29 Jul 2024 04:36:50 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYI7T-00000009xpY-0UPC for linux-arm-kernel@lists.infradead.org; Mon, 29 Jul 2024 04:36:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 34987FEC; Sun, 28 Jul 2024 21:36:47 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.10]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 329FA3F5A1; Sun, 28 Jul 2024 21:36:19 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, Anshuman Khandual Subject: [PATCH V2 0/3] aarch64: Enable access for FEAT_D128 registers in EL1/EL2 Date: Mon, 29 Jul 2024 10:06:03 +0530 Message-Id: <20240729043606.871451-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240728_213623_215645_0559B855 X-CRM114-Status: UNSURE ( 8.10 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series enables access for FEAT_D128 relevant registers in EL1/EL2 via setting respective bits in SCR_EL3, when their corresponding features are detected. -------------------------------------------------------------- | FEAT_D128 | ID_AA64MMFR3_EL1_D128 | SCR_EL3_D128En | | FEAT_SCTLR2 | ID_AA64MMFR3_EL1_SCTLRX | SCR_EL3_SCTLR2En | | FEAT_THE | ID_AA64PFR1_EL1_THE | SCR_EL3_RCWMASKEn | -------------------------------------------------------------- Changes in V2: - Moved up the patch related to SCTLR2_ELx from [PATCH 2/3] to [PATCH 1/3] - Updated the commit message for the above mentioned patch - Fixed the commit message s/D128En/SCTLR2En as the enabling bit - Reset SCTLR2_ELx registers so that unaware kernels do not get surprises Changes in V1: https://lore.kernel.org/all/20240723110630.483871-1-anshuman.khandual@arm.com/ Anshuman Khandual (3): aarch64: Enable access into SCTLR2_ELx registers from EL2 and below aarch64: Enable access into 128 bit system registers from EL2 and below aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below arch/aarch64/include/asm/cpu.h | 11 ++++++++++- arch/aarch64/init.c | 12 ++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-)