| Message ID | 20240731-arm-pmu-3-9-icntr-v3-0-280a8d7ff465@kernel.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | arm64: Add support for Armv9.4 PMU fixed instruction counter | expand |
On 31/07/2024 5:51 pm, Rob Herring (Arm) wrote: > This series adds support for the optional fixed instruction counter > added in Armv9.4 PMU. Most of the series is a refactoring to remove the > index to counter number conversion which dates back to the Armv7 PMU > driver. Removing it is necessary in order to support more than 32 > counters without a bunch of conditional code further complicating the > conversion. > > Patch 1 changes struct arm_pmu.num_events to a bitmap of events, and > updates all the users. This removes the index to counter conversion > on the PMUv3 and Armv7 drivers. > > Patch 2 updates various register accessors to use 64-bit values matching > the register size. > > Patches 3-4 update KVM PMU register accesses to use shared accessors > from asm/arm_pmuv3.h. > > Patches 5-6 rework KVM and perf PMU defines for counter indexes and > number of counters. > > Patch 7 finally adds support for the fixed instruction counter. > > I tested this on FVP with VHE host and a guest. Also ran kvm-unittests > in Arm's kernelCI. > I ran the Perf tests and poked around a bit with PMUs and chaining events (on non-fixed instruction counter hardware): Tested-by: James Clark <james.clark@linaro.org>
On Wed, 31 Jul 2024 10:51:17 -0600, Rob Herring (Arm) wrote: > This series adds support for the optional fixed instruction counter > added in Armv9.4 PMU. Most of the series is a refactoring to remove the > index to counter number conversion which dates back to the Armv7 PMU > driver. Removing it is necessary in order to support more than 32 > counters without a bunch of conditional code further complicating the > conversion. > > [...] Applied to will (for-next/perf), thanks! [1/7] perf: arm_pmu: Remove event index to counter remapping https://git.kernel.org/will/c/bf5ffc8c80e0 [2/7] perf: arm_pmuv3: Prepare for more than 32 counters https://git.kernel.org/will/c/a4a6e2078d85 [3/7] KVM: arm64: pmu: Use arm_pmuv3.h register accessors https://git.kernel.org/will/c/741ee5284551 [4/7] KVM: arm64: pmu: Use generated define for PMSELR_EL0.SEL access https://git.kernel.org/will/c/f9b11aa00708 [5/7] arm64: perf/kvm: Use a common PMU cycle counter define https://git.kernel.org/will/c/126d7d7cce5e [6/7] KVM: arm64: Refine PMU defines for number of counters https://git.kernel.org/will/c/2f62701fa5b0 [7/7] perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter https://git.kernel.org/will/c/d8226d8cfbaf Cheers,
This series adds support for the optional fixed instruction counter added in Armv9.4 PMU. Most of the series is a refactoring to remove the index to counter number conversion which dates back to the Armv7 PMU driver. Removing it is necessary in order to support more than 32 counters without a bunch of conditional code further complicating the conversion. Patch 1 changes struct arm_pmu.num_events to a bitmap of events, and updates all the users. This removes the index to counter conversion on the PMUv3 and Armv7 drivers. Patch 2 updates various register accessors to use 64-bit values matching the register size. Patches 3-4 update KVM PMU register accesses to use shared accessors from asm/arm_pmuv3.h. Patches 5-6 rework KVM and perf PMU defines for counter indexes and number of counters. Patch 7 finally adds support for the fixed instruction counter. I tested this on FVP with VHE host and a guest. Also ran kvm-unittests in Arm's kernelCI. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> --- Changes in v3: - Fix using 64-bit counters in pre-Armv8.5. The chained event check for cycle counter in armv8pmu_event_is_chained() was returning the cycle counter needed chaining which is never true. Separate fix is here: https://lore.kernel.org/all/20240710182357.3701635-1-robh@kernel.org/ - Rebase to v6.11-rc1 and dropped already applied patches - Link to v2: https://lore.kernel.org/r/20240626-arm-pmu-3-9-icntr-v2-0-c9784b4f4065@kernel.org Changes in v2: - Include threshold fix patches and account for threshold support in counter assignment. - Add patch including asm/arm_pmuv3.h from linux/perf/arm_pmuv3.h - Fix compile error for Apple PMU - Minor review comments detailed in individual patches - Link to v1: https://lore.kernel.org/r/20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org --- Rob Herring (Arm) (7): perf: arm_pmu: Remove event index to counter remapping perf: arm_pmuv3: Prepare for more than 32 counters KVM: arm64: pmu: Use arm_pmuv3.h register accessors KVM: arm64: pmu: Use generated define for PMSELR_EL0.SEL access arm64: perf/kvm: Use a common PMU cycle counter define KVM: arm64: Refine PMU defines for number of counters perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter arch/arm/include/asm/arm_pmuv3.h | 20 ++++++ arch/arm64/include/asm/arm_pmuv3.h | 53 ++++++++++++-- arch/arm64/include/asm/kvm_host.h | 8 +-- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/kvm/pmu-emul.c | 14 ++-- arch/arm64/kvm/pmu.c | 87 ++++++----------------- arch/arm64/kvm/sys_regs.c | 11 +-- arch/arm64/tools/sysreg | 30 ++++++++ drivers/perf/apple_m1_cpu_pmu.c | 4 +- drivers/perf/arm_pmu.c | 11 +-- drivers/perf/arm_pmuv3.c | 140 +++++++++++++++++++------------------ drivers/perf/arm_v6_pmu.c | 6 +- drivers/perf/arm_v7_pmu.c | 77 ++++++++------------ drivers/perf/arm_xscale_pmu.c | 12 ++-- include/kvm/arm_pmu.h | 8 +-- include/linux/perf/arm_pmu.h | 10 ++- include/linux/perf/arm_pmuv3.h | 9 ++- 17 files changed, 272 insertions(+), 229 deletions(-) --- base-commit: 8400291e289ee6b2bf9779ff1c83a291501f017b change-id: 20240607-arm-pmu-3-9-icntr-04375ddd0082 Best regards,