From patchwork Wed Jul 31 16:51:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13748976 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24376C3DA7F for ; Wed, 31 Jul 2024 16:52:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To: Content-Transfer-Encoding:Content-Type:MIME-Version:Message-Id:Date:Subject: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=BCh1tyq63oQ/NhI/c+RNUb68oLFIl1pJvDn742DlHvw=; b=YQFxMbnzcE0QnK UlQ11n+zDTHnB55cTMPme40gfOQkNxO4BzjTxEKt9WoMxNWjqfdp9YKC7UYpNw0lTascWIiCbFkHN MotHviBhvjwFRYtozepGsyZRx4lro27Kqga34gMbXBW2scLy5sUZT2nYWKS3uaVaPlbYH/RcJ864t vH4Gm6/Ss49viVAfkCisX7E55x0XMwrUkWOFgUY+YJ6cj5DfYu0CDgFIzo8hn7ZY2BAoLbEC2ERMc tTp/ePJ8bxqxSGtgEbRMNWAlH668RbIU/zNw/3iJQXYjmAeg4rnIe9jIamSucjJKvYEWj0wsVPt0k DbmmekE9I7IK4uscZf5A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZCYe-00000001v77-0sGS; Wed, 31 Jul 2024 16:52:12 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZCY9-00000001uxq-159U for linux-arm-kernel@lists.infradead.org; Wed, 31 Jul 2024 16:51:43 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 4007FCE16F2; Wed, 31 Jul 2024 16:51:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D84E4C116B1; Wed, 31 Jul 2024 16:51:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722444698; bh=a3N1jdJkjGQcJ3ZzY05M9xZbajIj8LwGdUK1HF2vmvM=; h=From:Subject:Date:To:Cc:From; b=iAeVyuNoztqPUGoDanPeAcyu7Ve54IKxX4KN/dntZHo3z5MbsuDnY8Ju3bdLl2tQz JpvpSsPEZn4MadFMaSGCS7lNbZz54aIrH0bpoMDI98ADKC6RCSnvemigwpRxj15Pbq R7fPltHSBJvjig4qvhwRyma6fys1jAJGzRbW9wC5R1VVSeFG5qcwhT1Y+dexn5K8It kGIE2fuvcsi/IuQSQt3yxUPpGVy/N+QFAnODhdCIIzlswW/wRR2FtNlEnBdervg07u fovGFErtcmLgC1cRHwmcXILoqEUw7mgLP3mNfTlOAZO9tf/x7pUuQXn/bL7MazzYkD oTbP6nQRfCMHA== From: "Rob Herring (Arm)" Subject: [PATCH v3 0/7] arm64: Add support for Armv9.4 PMU fixed instruction counter Date: Wed, 31 Jul 2024 10:51:17 -0600 Message-Id: <20240731-arm-pmu-3-9-icntr-v3-0-280a8d7ff465@kernel.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAIVrqmYC/33NSw6CMBCA4auQrh1T2kLBlfcwLqAPaJRCpthoC He3sNLEuPwnM98sJBh0JpBTthA00QU3+hT8kBHVN74z4HRqwigTtKQSGhxgGh7AoQan/IxABZe F1prSipF0N6Gx7rmbl2vq3oV5xNf+Iubb9J8Wc6CgZKuZVsZa3p5vBr25H0fsyMZF9kGw8hfBN qKWlWiFTUvFF7Gu6xvBKQEc9gAAAA== To: Will Deacon , Marc Zyngier , Mark Rutland , James Clark , James Morse , Suzuki K Poulose , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Oliver Upton , Zenghui Yu Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.15-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240731_095141_692758_5275A3B2 X-CRM114-Status: GOOD ( 15.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series adds support for the optional fixed instruction counter added in Armv9.4 PMU. Most of the series is a refactoring to remove the index to counter number conversion which dates back to the Armv7 PMU driver. Removing it is necessary in order to support more than 32 counters without a bunch of conditional code further complicating the conversion. Patch 1 changes struct arm_pmu.num_events to a bitmap of events, and updates all the users. This removes the index to counter conversion on the PMUv3 and Armv7 drivers. Patch 2 updates various register accessors to use 64-bit values matching the register size. Patches 3-4 update KVM PMU register accesses to use shared accessors from asm/arm_pmuv3.h. Patches 5-6 rework KVM and perf PMU defines for counter indexes and number of counters. Patch 7 finally adds support for the fixed instruction counter. I tested this on FVP with VHE host and a guest. Also ran kvm-unittests in Arm's kernelCI. Signed-off-by: Rob Herring (Arm) Tested-by: James Clark --- Changes in v3: - Fix using 64-bit counters in pre-Armv8.5. The chained event check for cycle counter in armv8pmu_event_is_chained() was returning the cycle counter needed chaining which is never true. Separate fix is here: https://lore.kernel.org/all/20240710182357.3701635-1-robh@kernel.org/ - Rebase to v6.11-rc1 and dropped already applied patches - Link to v2: https://lore.kernel.org/r/20240626-arm-pmu-3-9-icntr-v2-0-c9784b4f4065@kernel.org Changes in v2: - Include threshold fix patches and account for threshold support in counter assignment. - Add patch including asm/arm_pmuv3.h from linux/perf/arm_pmuv3.h - Fix compile error for Apple PMU - Minor review comments detailed in individual patches - Link to v1: https://lore.kernel.org/r/20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org --- Rob Herring (Arm) (7): perf: arm_pmu: Remove event index to counter remapping perf: arm_pmuv3: Prepare for more than 32 counters KVM: arm64: pmu: Use arm_pmuv3.h register accessors KVM: arm64: pmu: Use generated define for PMSELR_EL0.SEL access arm64: perf/kvm: Use a common PMU cycle counter define KVM: arm64: Refine PMU defines for number of counters perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter arch/arm/include/asm/arm_pmuv3.h | 20 ++++++ arch/arm64/include/asm/arm_pmuv3.h | 53 ++++++++++++-- arch/arm64/include/asm/kvm_host.h | 8 +-- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/kvm/pmu-emul.c | 14 ++-- arch/arm64/kvm/pmu.c | 87 ++++++----------------- arch/arm64/kvm/sys_regs.c | 11 +-- arch/arm64/tools/sysreg | 30 ++++++++ drivers/perf/apple_m1_cpu_pmu.c | 4 +- drivers/perf/arm_pmu.c | 11 +-- drivers/perf/arm_pmuv3.c | 140 +++++++++++++++++++------------------ drivers/perf/arm_v6_pmu.c | 6 +- drivers/perf/arm_v7_pmu.c | 77 ++++++++------------ drivers/perf/arm_xscale_pmu.c | 12 ++-- include/kvm/arm_pmu.h | 8 +-- include/linux/perf/arm_pmu.h | 10 ++- include/linux/perf/arm_pmuv3.h | 9 ++- 17 files changed, 272 insertions(+), 229 deletions(-) --- base-commit: 8400291e289ee6b2bf9779ff1c83a291501f017b change-id: 20240607-arm-pmu-3-9-icntr-04375ddd0082 Best regards,