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[0/3] arm64: dts: mediatek: mt8195: Fix and clean up xhci1

Message ID 20240731034411.371178-1-wenst@chromium.org (mailing list archive)
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Series arm64: dts: mediatek: mt8195: Fix and clean up xhci1 | expand

Message

Chen-Yu Tsai July 31, 2024, 3:44 a.m. UTC
Hi everyone,

This series fixes and cleans up the representation of xhci1, whether
used in USB 2.0 only or USB 2.0 + 3.0 designs. This work is a result
of discussions from the original Kernel CI report [1] on xhci1 failing
to probe, and subsequent patches [2][3].

Patch 1 explicitly disables USB 3.0 on the Cherry design. The super
speed pairs are used for PCIe instead.

Patch 2 does the same for the Radxa Nio 12L.

Patch 3 rearranges the PHY assignment such that the default links both
USB 2.0 and USB 3.0 PHYs to the controller, and designs using only
USB 2.0 will override the PHY assignment and disable USB 3.0 together.

The first two patches are fixes and marked for stable. The third is
more of a cosmetic change.

Please have a look and merge.


Thanks
ChenYu


[1] https://lore.kernel.org/all/9fce9838-ef87-4d1b-b3df-63e1ddb0ec51@notapiano/
[2] https://lore.kernel.org/linux-mediatek/20240711093230.118534-1-angelogioacchino.delregno@collabora.com/
[3] https://lore.kernel.org/linux-mediatek/20240722-usb-1129-probe-pci-clk-fix-v1-1-99ea804228b6@collabora.com/

Chen-Yu Tsai (3):
  arm64: dts: mediatek: mt8195-cherry: Mark USB 3.0 on xhci1 as disabled
  arm64: dts: mediatek: mt8395-nio-12l: Mark USB 3.0 on xhci1 as
    disabled
  arm64: dts: mediatek: mt8195: Assign USB 3.0 PHY to xhci1 by default

 arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi               | 2 ++
 arch/arm64/boot/dts/mediatek/mt8195.dtsi                      | 2 +-
 arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts        | 2 --
 arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts | 1 +
 arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts         | 2 ++
 5 files changed, 6 insertions(+), 3 deletions(-)

Comments

AngeloGioacchino Del Regno July 31, 2024, 8:19 a.m. UTC | #1
On Wed, 31 Jul 2024 11:44:07 +0800, Chen-Yu Tsai wrote:
> This series fixes and cleans up the representation of xhci1, whether
> used in USB 2.0 only or USB 2.0 + 3.0 designs. This work is a result
> of discussions from the original Kernel CI report [1] on xhci1 failing
> to probe, and subsequent patches [2][3].
> 
> Patch 1 explicitly disables USB 3.0 on the Cherry design. The super
> speed pairs are used for PCIe instead.
> 
> [...]

Applied to v6.11-next/dts64, thanks!

[1/3] arm64: dts: mediatek: mt8195-cherry: Mark USB 3.0 on xhci1 as disabled
      commit: 09d385679487c58f0859c1ad4f404ba3df2f8830
[2/3] arm64: dts: mediatek: mt8395-nio-12l: Mark USB 3.0 on xhci1 as disabled
      commit: be985531a5dd9ca50fc9f3f85b8adeb2a4a75a58
[3/3] arm64: dts: mediatek: mt8195: Assign USB 3.0 PHY to xhci1 by default
      commit: fe035fa6f56c5b8146fcfe4253edbb9e9399ce2d

Cheers,
Angelo