| Message ID | 20240801101803.1982459-1-mark.rutland@arm.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | arm64: errata: Expand speculative SSBS workaround (again) | expand |
On Thu, 01 Aug 2024 11:18:00 +0100, Mark Rutland wrote: > A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS > special-purpose register does not affect subsequent speculative > instructions, permitting speculative store bypassing for a window of > time. > > We worked around this for a number of CPUs in commits: > > [...] Applied to arm64 (for-next/fixes), thanks! [1/3] arm64: cputype: Add Cortex-X1C definitions https://git.kernel.org/arm64/c/58d245e03c32 [2/3] arm64: cputype: Add Cortex-A725 definitions https://git.kernel.org/arm64/c/9ef54a384526 [3/3] arm64: errata: Expand speculative SSBS workaround (again) https://git.kernel.org/arm64/c/adeec61a4723
Hi, A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS special-purpose register does not affect subsequent speculative instructions, permitting speculative store bypassing for a window of time. We worked around this for a number of CPUs in commits: * 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") * 75b3c43eab594bfb ("arm64: errata: Expand speculative SSBS workaround") Since then, similar errata have been published for a number of other Arm Ltd CPUs, for which the same mitigation is sufficient. These patches expand the existing workaround to cover those CPUs. Mark. Mark Rutland (3): arm64: cputype: Add Cortex-X1C definitions arm64: cputype: Add Cortex-A725 definitions arm64: errata: Expand speculative SSBS workaround (again) Documentation/arch/arm64/silicon-errata.rst | 18 +++++++++++++++++ arch/arm64/Kconfig | 22 +++++++++++++++------ arch/arm64/include/asm/cputype.h | 4 ++++ arch/arm64/kernel/cpu_errata.c | 11 ++++++++++- 4 files changed, 48 insertions(+), 7 deletions(-)