From patchwork Thu Aug 8 04:14:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 13756936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF664C3DA4A for ; Thu, 8 Aug 2024 04:15:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To: Content-Transfer-Encoding:Content-Type:MIME-Version:Message-Id:Date:Subject: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=n3sZ4FsOpgBw2cpkxzXazcULuROCyRckfFE8WrKc23c=; b=LXKAm8+PEiVxxO N7QCu8T9EPpLjvaXTlm1f4gMLzSM1+Kl6EYUqQ07XtE9S6KHRMoD5Yk0ISCFINqMP87TtzzzlRkni 4rs59l/3coTyAPk4SN2W1+nVZBJLXJWJZHquQF9j5TKEp/d02JuedGA6vPNUg6mZgpbpIaRxEsvAw 3gDHKnEMXZngR6mmwk+utgXUOpLyw3TWPGFUSEc2P9iLK44D5oCyBClIGEmicoYjn4quJBqV1cJgI S2C2GN+JiuugJHlM3O4LkfpeTXRPw1OaC4tMEGkuUVz3XvIbtUOPMG6B8nTsKkE2cBKdOdF9sP3Dj cTguY3SNlczn2aUa88Yg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sbuYj-00000006zuo-2ZDL; Thu, 08 Aug 2024 04:15:29 +0000 Received: from pi.codeconstruct.com.au ([203.29.241.158] helo=codeconstruct.com.au) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sbuY4-00000006zgz-07rr for linux-arm-kernel@lists.infradead.org; Thu, 08 Aug 2024 04:14:49 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=codeconstruct.com.au; s=2022a; t=1723090486; bh=n3sZ4FsOpgBw2cpkxzXazcULuROCyRckfFE8WrKc23c=; h=From:Subject:Date:To:Cc; b=AR/nq4T3O36j2aPSH1YxOzliZ0Qdgq9WcseuCgPmIupAGuOvs7srJsccs9k33u6Ie 5vbN65GDaqWjfSoiCeNBdmbcRAT0wgJvHfYqonn6Dz1BPTsww7BuvDFEpMnwTmsth0 od7cGfbOdG8EHRvatmlXdLtHFGHeAVERDJKHkVLti1A4oxCT29tNeBM0WfWJfUhX5L OPpJSqWN+dtEn15bpHag+HNMPW4rOkHyl9Y7SK2buA9CFAMyKJ7yyCCBXyEgFSr5Ih STAx3nryVgYzW2dnKMcCMNY72yisErw2BO/70gFlE63UU4PviL87REmXQjcKULHbg6 VfcUOQdxSUKqQ== Received: from [127.0.1.1] (203-57-213-111.dyn.iinet.net.au [203.57.213.111]) by mail.codeconstruct.com.au (Postfix) with ESMTPSA id 65FFE654E9; Thu, 8 Aug 2024 12:14:45 +0800 (AWST) From: Andrew Jeffery Subject: [PATCH v2 0/2] dt-bindings: interrupt-controller: Convert Aspeed (C)VIC to DT schema Date: Thu, 08 Aug 2024 13:44:23 +0930 Message-Id: <20240808-dt-warnings-irq-aspeed-dt-schema-v2-0-c2531e02633d@codeconstruct.com.au> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAB9GtGYC/5WNQQ6DIBAAv2I4dw1SNLan/qPxQNhV9yBYQNvG+ PeiP+hx5jCziUiBKYp7sYlAK0f2LoO6FMKOxg0EjJmFkkrLVirABG8THLshAocXmDgT4aGjHWk yUPc19VijvlZG5MwcqOfPuXh2mUeOyYfveVyrw/4RXyuQ0FrUqmlQyZt+WI9kvYspLDaV1k+lW US37/sPWyakwtsAAAA= To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org X-Mailer: b4 0.14.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240807_211448_319951_E2181222 X-CRM114-Status: UNSURE ( 9.17 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, This short series converts the Aspeed VIC and CVIC bindings over to DT schema. The CVIC has historically been documented under "misc" as it's the interrupt controller for the Coldfire co-processor embedded in the SoCs, and not for the main ARM core. Regardless, I've updated both in this series. I tried to document the historical oddities and conversion quirks in the commit messages where appropriate. Please review! Andrew --- Changes in v2: - Address feedback from Krzysztof - https://lore.kernel.org/r/c51fb027-f8bd-4b10-b9c0-dbbe8e8cf4c1@kernel.org/ - https://lore.kernel.org/r/ec19fe07-84bd-4c32-a886-e6126af52f4c@kernel.org/ - Address feedback from Rob - https://lore.kernel.org/r/20240806172917.GA1836473-robh@kernel.org/ - Link to v1: https://lore.kernel.org/r/20240802-dt-warnings-irq-aspeed-dt-schema-v1-0-8cd4266d2094@codeconstruct.com.au --- Andrew Jeffery (2): dt-bindings: interrupt-controller: aspeed,ast2400-vic: Convert to DT schema dt-bindings: misc: aspeed,ast2400-cvic: Convert to DT schema .../interrupt-controller/aspeed,ast2400-vic.txt | 23 -------- .../interrupt-controller/aspeed,ast2400-vic.yaml | 62 ++++++++++++++++++++++ .../bindings/misc/aspeed,ast2400-cvic.yaml | 60 +++++++++++++++++++++ .../devicetree/bindings/misc/aspeed,cvic.txt | 35 ------------ 4 files changed, 122 insertions(+), 58 deletions(-) --- base-commit: 8400291e289ee6b2bf9779ff1c83a291501f017b change-id: 20240802-dt-warnings-irq-aspeed-dt-schema-5f5efd5d431a Best regards,