From patchwork Thu Aug 22 10:14:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13773181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3AC3C5320E for ; Thu, 22 Aug 2024 10:16:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=LyRwJemUbaAksJ7+UhNvykHMCjL2Qur+oXPiXU2zm9E=; b=fAD3P9QGjBs6rxwEfmchOFwPAA ERvsEvicZpXZ2VtrMYWBmzvwHisaKo5UdyX+o4F1w9DYCpGyp9ne4Nfa8zk6cl1M5MgZ/vg5v9tLx xzmaa1ZAe3mtBRd9DQkDsGbJxEBSEPVN2NToSDySVoZMGGNDsa9HlwgMoMOeKpZpvST2R8K75KONO 1V0/8Et/4dG5fXkCbMZF5Yulvf2RaIUipCIAmN1RYwEPdpflvP1qOuZQ9OZ6sRs50nfPOlYTPn+Dj pcrw+cEfT/l+MhfeGJLQ8TSM69Z7A8RV6osUHNiBg0/2QmZbwA24D02ObgQ+O1zT7HJnQ5ooE3fQ+ qKikD5FA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4rp-0000000COTa-3dkA; Thu, 22 Aug 2024 10:16:33 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sh4qM-0000000COGZ-2tdT for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2024 10:15:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3F6F7DA7; Thu, 22 Aug 2024 03:15:26 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C54813F66E; Thu, 22 Aug 2024 03:14:58 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: akos.denke@arm.com, andre.przywara@arm.com, luca.fancellu@arm.com, mark.rutland@arm.com, maz@kernel.org Subject: [BOOT-WRAPPER v3 00/10] Cleanup initialization Date: Thu, 22 Aug 2024 11:14:31 +0100 Message-Id: <20240822101441.251184-1-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240822_031502_802071_DDECAF55 X-CRM114-Status: UNSURE ( 9.43 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org These patches cleanup the boot-wrapper initialization logic to make it more consistent and easier to extend in C code in future. The big changes are: * The kernel is always entered via an exception return. This allows us to initialize PSTATE consistently, and will allow us to adjust the SPSR dynamically in C code in future if necessary. * Regardless of the entered exception level, CPU state is initialized under cpu_init_arch(), allowing for logic to be shared regardless of which exception level was entered. * CPUs are initialized sequentially, which allows better for better logging within the boot-wrapper. Since v1 [1]: * Retain SPSR.T bit handling; necessary for PSCI * Comment on handling of CNTFRQ_EL0 when not entered at the highest EL * Fix missing braces in cpu_init_psci_arch() * Add Marc's Acked-by tag series-wide Since v2 [2]:A * Cleanup commit messages and comments * Cleanup AArch32 exception return * Remove per-cpu "Done" message * Add Andre's Reviewed-by tags [1] https://lore.kernel.org/linux-arm-kernel/20240729161501.1806271-1-mark.rutland@arm.com/ [2] https://lore.kernel.org/linux-arm-kernel/20240812101555.3558589-1-mark.rutland@arm.com/ Mark. Mark Rutland (10): aarch64: Remove redundant EL1 entry logic aarch64: Implement cpu_init_arch() aarch64: Always enter kernel via exception return aarch32: Refactor inital entry aarch32: Implement cpu_init_arch() aarch32: Always enter kernel via exception return Unify assembly setup paths Simplify spin logic Add printing functions Boot CPUs sequentially arch/aarch32/boot.S | 95 +++++++++++--------- arch/aarch32/include/asm/{gic-v3.h => gic.h} | 2 +- arch/aarch32/init.c | 30 +++++-- arch/aarch64/boot.S | 64 ++++--------- arch/aarch64/include/asm/{gic-v3.h => gic.h} | 2 +- arch/aarch64/init.c | 30 +++++-- arch/aarch64/spin.S | 19 +--- common/boot.c | 20 ++--- common/gic-v3.c | 2 +- common/gic.c | 2 +- common/init.c | 48 ++++++++-- common/platform.c | 35 ++++++++ common/psci.c | 16 +--- include/boot.h | 8 +- include/gic.h | 16 ++++ include/platform.h | 4 + 16 files changed, 222 insertions(+), 171 deletions(-) rename arch/aarch32/include/asm/{gic-v3.h => gic.h} (91%) rename arch/aarch64/include/asm/{gic-v3.h => gic.h} (92%) create mode 100644 include/gic.h